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Preliminary
Features
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HT9580 Character Pager Controller
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Operating voltage: 2.4V~3.5V Temperature range: -30C to +85C low power, high performance M6502 core low power crystal oscillator control - 512/1200/2400 bps data rate operation CCIR Radio Paging Code No.1 (POCSAG) compatible 76.8kHz crystal for all available data rates High/low system clock switching capability 44 Kbytes program ROM 848 bytes global data RAM Internal 2 Mbits Character ROM 256 Kbits internal SRAM External option up to 2 Mbits Character ROM or 2 Mbits SRAM SED15X(KSX), MC141X and HD66410 series LCD driver compatible interface option 46 bytes message buffer One 16-bit timer and one 8-bit timer
Internal 2Hz or 1Hz RTC or Real Time Clock option Single buzzer generator output (BZ) with duty cycle control low current HALT mode operation 16-bit watchdog timer Built-in data filter (16-times over-sampling ) and bit clock recovery Advanced synchronization algorithm 2-bit random and (optional) 4-bit burst error correction for address and message Up to 6 user addresses and 6 user frames, independently programmable 3 RF power-on timing control pins and Received data inversion (optional) Built in SPI circuit Out-of-range condition indicator One internal 8-bit D/A converter Battery fail and battery low detection 80-pin LQFP package
General Description
The HT9580 is a high performance pager controller which can be used for Chinese Pager system applications. The HT9580 4-in-1 Character Pager Controller combines a POCSAG decoder with a M6502 microprocessor core, 2 Mbits Character ROM and 256 Kbits SRAM to provide both high decoder performance and excellent system flexibility. The decoder utilizes a 2-bit random error correction algorithm and therefore provides excellent decoder sensitivity. The controller contains a full function pager decoder at a 512, 1200, 2400 bps data rates. Using an M6502 core takes advantage of a flexible external control interface, LCD driver chips and abundant programming resources from worldwide providers. The internal SPI would communicate with SPI of FLEXTM high speed pager decoder.
FLEX
TM
is a trademark of Motorola Inc.
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April 28, 2000
Preliminary
Block Diagram
R e g is te r S e c tio n C o n tr o l S e c tio n
HT9580
R E S IR Q
NMI
L o g ic
RESET IR Q
In d e x R e g is te r Y A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 D a ta B u s B u ffe r Legend = 8 B it L in e = 1 B it L in e M 6 5 0 2 C o re ABH In te rn a l A D L ABL In te rn a l A D L In d e x R e g is te r X S ta c k P o in t R e g is te r ( s ) ALU
In te rru p t L o g ic
NMI VP
RDY SYNC
ML
In s tr u c tio n D ecoder S p e c ia l B u s T im in g C o n tro l
A c c u m u la to r A PCL PCH In p u t D a ta L a tc h (D L )
P ro c e s s o r S ta tu s R e g is te r P
C lo c k G e n e ra to r/ O s c illa to r
P H I2 (IN ) P H I1 (O U T ) P H I2 (O U T ) SO R /W BE
OSC1 OSC2
In te rru p t L o g ic D0 D1 D2 D3 D4 D5 D6 D7
RA1 RA1 RA1 RA1 5 6 7 P_M O DE LCD_E LCD_RW LCD_CS0 LCD_CS1 LCD_CL LCD_A0
A d d re s s D ecoder
P ro g ra m ROM
SRAM
MUX
4
T M R 0 ( 8 b it)
P r e - s c a le r
X1 S y s te m X1 S y s te m C lo c k TM R1 PA0~PA5 PB0~PB7 PC 0~PC 1 C lo c k
C h a ra c te r ROM LCD D r iv e r In te rfa c e W DT
PAC PBC PCC T o n e G e n e ra to r
PA PB PC D u ty C y c le C o n tr o l
MUX
T M R 1 ( 1 6 b it)
MUX
BZ
RSSI
RTC
BAF
D ig ita l F ilte r
D a ta P h a s e R e c o v e ry
RF Power C o n tr o lle r U s e r A d d re s s and C o n fig u r a tio n M e m o ry D ecoder D a ta O u tp u t C o n tro l
SPI C ir c u it
B S 1 /S S B S 2 /S C K B S 3 /M O S I D I/M IS O B A L /S R D Y
D A_O U T
8 - b it D /A
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
BC H C ode D ecoder S ta tu s C o n tr o lle r POCSAG
S P I C o n tro l
X1 X2
D ecoder
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April 28, 2000
Preliminary
Pin Assignment
RSSI D I/M IS O B S 3 /M O S I B S 2 /S C K B S 1 /S S TS PA5 PA4 PA3 PA2 PA1 PA0 RESET TSC TS1 OSC2 OSC1 VSS X2 61 DA BA SR VS VD BZ PC PC PB PB PB PB PB PB PB PB TM A0 A1 A2 F S D 1 7 6 5 4 3 2 1 0 R1 0 _O U T D Y /B A L
HT9580
X1 80 1
VDD LCD_CS1 LCD_CS0 LCD_CL LCD_A0 LCD_RW LCD_E D7 D6 D5 D4 D3 D2 D1 D0 R /W SR AM _C E M ASK_CE OE PSEN
60
HT9580 80 LQ FP
20 21
41 40
A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 VSS P_M VDD RA1 RA1 RA1 RA1 7 ODE 6 5 4
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April 28, 2000
Preliminary
Pin Description
Pin No. 1, 25, 56 2 3 4 5 6 7 15~8 16 17 Pin Name VDD LCD_CS1 LCD_CS0 LCD_CL LCD_A0 LCD_RW LCD_E D0~D7 R/W SRAM_CE I/O 3/4 O O O O O O I/O O O Positive power supply LCD driver chip select control (for slave LCD driver) LCD driver chip select control (for master LCD driver) LCD driver clock output LCD driver data/command select control LCD Driver Read/Write signal output LCD driver enable clock control 8-bit, tristate, bidirectional I/O data bus. Read/Write signal output Description
HT9580
SRAM chip Enable. This signal is generated from the HT9580 to provide read or write timing for external SRAM devices. (See Application Circuit) Mask ROM Chip Enable. This signal is generated from the HT9580 to provide read timing for external Mask ROM devices. (See Application Circuit) Mask ROM or SRAM Output Enable. This signal is generated from the HT9580 to provide read timing for external Mask ROM and SRAM devices. (See Application Circuit) Program Store Enable. This pin is used to connect the OE and CE pins of the external 44 Kbytes program ROM when the MODE_P internal pad is connected to VSS. (See note) Extended address bus pins Internal or external program ROM selection without pull-high resistor. If the pin connects to VDD, the internal program ROM will be fetched (normal type), otherwise the external program ROM will be fetched when the pin connects to VSS (Romless). Negative power supply Address bus pins. This is used for memory and I/O exchanges on the data bus. Schmitt trigger input for timer1 counter with pull-high resisor. General Input/Output Port B. The input cell structures can be selected as CMOS or CMOS with pull-high resistors. General Input/Output Port C. The input cell structures can be selected as CMOS or CMOS with pull-high resistors. Buzzer non-inverting BZ output
18
MASK_CE
O
19
OE
O
20 21~24 26
PSEN RA17~RA14 P_MODE
O O I 3/4 O I I/O I/O O
27, 57, 78 VSS 43~28 44 45~52 53~54 55 A0~A15 TMR1 PB0~PB7 PC0~PC1 BZ
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April 28, 2000
Preliminary
Pin No. Pin Name BAL 58 I/O I Description Battery voltage detector input with pull-high resistor.
HT9580
SRDY
I
SPI slave ready 3/4 This slave ready pin is a Schmitt trigger input with pull-high resistor. When the slave initiates the SPI transfer, a high to low transition activates an interrupt. When the master initiates the SPI transfer, a high to low transition trigger the master to start the transfer. Battery fail indication input, active low. D/A converter output. This pin is an 8-bit D/A analog output RSSI output from IF circuit. This pin should be pulled high or low externally when this pin is not used. POCSAG code input serial data. CMOS input with pull-high resistor. SPI master-in-slave-out 3/4 this is the data input with pull-high resistor for SPI communications. PLL power control enable, CMOS output SPI master-out-slave-in 3/4 this is the data output for SPI communications. RF quick charge control enable, CMOS output SPI serial clock 3/4 the SCK signal is used to synchronize the data transfer. If HT9580 is in the master mode, the SCK is output clock. Otherwise, SCK is input clock if HT9580 is in the slave mode. Pager receiver power control enable output, CMOS output SPI slave select 3/4 this signal is used to enable the SPI slave for transfer. Decoder test mode input pin, active low with pull-high resistor. General Input/Output Port A. These ports can be programmed to have a wake-up capability for applications in keyboard operations or as normal I/O. Also the input cell structures are all Schmitt trigger types and can be selected between CMOS or CMOS with pull-high resistors. Schmitt trigger reset input, active low. mC test mode input pin, active low with internal pull-high resistor. The test circuit will be activated when this pin pulls low. Decoder test mode input pin, active low with pull-high resistor. The internal test mode will be activated when this pin pulls low. OSC1 and OSC2 are connected to an RC network to form a main clock oscillator X1 and X2 are connected to a crystal to form an internal low power clock oscillator (32.768kHz, 76.8kHz, or 153.6kHz)
59 60 61
BAF DA_OUT RSSI DI
I O I I I O O O I/O O O I
62 MISO BS3 63 MOSI BS2 64 SCK BS1 65 66 SS TS
72~67
PA0~PA5
I/O
73 74 75 77 76 80 79
RESET TSC TS1 OSC1 OSC2 X1 X2
I I I I O I O
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April 28, 2000
Preliminary
Absolute Maximum Ratings
Supply Voltage..............................-0.3V to 3.6V Input Voltage .................VSS-0.5V to VDD+0.5V
HT9580
Storage Temperature.................-55C to 150C Operating Temperature ..............-30C to 85C
Current Drain Per Pin Excluding VDD and VSS ............................................................................10mA Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol VDD IDD ISTP VIL VIH VIL1 VIH1 VIL2 VIH2 VOL VOH IOL IOH IOL1 IOH1 IOL2 IOH2 ROSC RPH Parameter Operating Voltage Operating Current HALT Mode Current Input low Voltage for I/O Port Input High Voltage for I/O Port Input low Voltage Input High Voltage Input low Voltage (BAF) Input High Voltage (BAF) Output low Voltage Output High Voltage I/O Port Sink Current I/O Port Source Current BZ, PC0~PC1 Sink Current BZ, PC0~PC1 Source Current BS1, BS2, BS3 Sink Current RC Oscillator Resistor I/O Port Pull-high Resistance Test Conditions VDD 3/4 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V Conditions 3V application No load, OSC1=1MHz fX1=76.8kHz No load, mC clock stop, fX1=76.8kHz 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 VOL=0.3V VOH=2.7V VOL=0.3V VOH=2.7V VOL=0.3V VOH=2.7V fOSC=1MHz 3/4 Min. 2.4 3/4 3/4 0 0.7VDD 0 0.7VDD 0 1.0 3/4 2.3 2.0 -1.2 2 -1.5 350 -1.0 3/4 100 Typ. 3.0 300 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3.6 -2.2 4.5 -2.5 3/4 3/4 51 250
Ta=25C Max. 3.5 3/4 100 0.3VDD 3 0.3VDD 3 0.9 3 0.4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Unit V mA mA V V V V V V V V mA mA mA mA mA mA kW kW
BS1, BS2, BS3 Source Current 3V
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April 28, 2000
Preliminary
A.C. Characteristics
Symbol fOSC1 DOSC1 fX1 tRESET Parameter Main Clock (RC OSC) Main Clock Duty Cycle Pager Clock Input (Crystal OSC) RESET Input Pulse Width Test Conditions VDD Conditions 3V 3V 3V 3/4 3/4 3/4 3/4 3/4 Min. 76.8 40 32.768 1 Typ. 1000 50 76.8 3/4
HT9580
Ta=25C Max. 2000 60 153.6 3/4 Unit kHz % kHz ms
Functional Description
Memory map
0000H 003BH 0040H 006DH 0080H 01CFH 01D0H 01FFH 0200H 03FFH 1000H In te r n a l/E x te r n a l C h a ra c te r R O M 8 K b y te s 2FFFH 3000H In te r n a l/E x te r n a l SRAM 8 K b y te s 4FFFH 5000H 2FFFH B a n k 0 ~ B a n k 3 1 ( 2 M b its ) I/O a n d D a ta S p a c e 6 0 B y te s M e s s a g e B u ffe r 4 6 B y te s G lo b a l D a ta M e m o r y 3 3 6 B y te s S ta c k s 4 8 B y te s G lo b a l D a ta M e m o r y 5 1 2 B y te s 2FFFH B a n k 0 ~ B a n k 3 1 ( 2 M b its ) 1000H 1000H In te rn a l C h a ra c te r R O M S pace (B a n k 0 ) 8 K b y te s
E x te rn a l C h a ra c te r R O M S pace (B a n k 0 ) 8 K b y te s
P ro g ra m R O M S p a c e 2 8 K B y te s
3000H
te rn a l RAM pace ank 0) 8 K b y te s
In S S (B
BFFFH C000H
4FFFH B a n k 0 ~ B a n k 3 (3 2 K B y te s ) P ro g ra m R O M S p a c e 1 6 3 7 8 B y te s 3000H
FFFAH FFFBH FFFCH FFFDH FFFEH FFFFH
N M I-L N M I-H R E S E T -L R E S E T -H IR Q -L IR Q -H 4FFFH
E x te rn a l SRAM S pace (B a n k 0 ) 8 K b y te s
B a n k 0 ~ B a n k 3 1 (2 5 6 K B y te s )
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April 28, 2000
Preliminary
HT9580 memory mapping table (I/O and data space)
Address 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH 000FH 0010H 0011H 0012H 0013H 0014H 0015H 0016H 0017H 0018H 0019H 001AH~ 002EH 002FH 0030H 0031H 0032H 0033H 0034H 0035H 0036H 0037H 0038H 0039H 003AH 003BH Register Name Config. WDT-TMR CLR WDT BZ-L BZ-H INT ctrl INT flag TMRC TMR1L TMR1H TMR0 PA data PB data PC data PAC PBC PCC PA WUE PA IM PB IM PC IM MROM-BP SRAM-BP LCD_CTRL LCD_CMD Decoder Control/ flag Decoder Configuration Memory D/A-L D/A-H Buffer Status SPI-CONFIG SPI-SPEED SPI-OUT3 SPI-OUT2 SPI-OUT1 SPI-OUT0 SPI-IN3 SPI-IN2 SPI-IN1 SPI-IN0 DA7 X MSG_END S/M SP7 D7 D7 D7 D7 D7 D7 D7 D7 DA6 X X LEN1 SP6 D6 D6 D6 D6 D6 D6 D6 D6 DA5 X count_5 LEN0 SP5 D5 D5 D5 D5 D5 D5 D5 D5 DA4 X count_4 REQST SP4 D4 D4 D4 D4 D4 D4 D4 D4 DA3 X count_3 SPIFG SP3 D3 D3 D3 D3 D3 D3 D3 D3 DA2 D/A_PD count_2 CLK_EDG SP2 D2 D2 D2 D2 D2 D2 D2 D2 DA1 RSSI count_1 SPI_EN SP1 D1 D1 D1 D1 D1 D1 D1 D1 DA0 BAT count_0 START SP0 D0 D0 D0 D0 D0 D0 D0 D0 Bit 7 HALT X X BZL7 BZH7 0 0 TMR1MOD TM1D7 TM1D15 TM0D7 X PB7 X X PBC7 X X X PBIM7 X BP_MODS1 LCD_D7 X Bit 6 CLK_SEL X X BZL6 BZH6 0 RTC_FG X TM1D6 TM1D14 TM0D6 X PB6 X X PBC6 X X X PBIM6 X BP_MODS0 LCD_D6 BL Bit 5 OSC_MOD X BZL5 BZH5 0 DR_FG TM1D5 TM1D13 TM0D5 PA5 PB5 X PAC5 PBC5 X PAWUE5 PAIM5 PBIM5 X M_BP5 S_BP5 LCD-CLK LCD_D5 OR Bit 4 LPM X BZL4 BZH4 RTCEN BF_FG TM1D4 TM1D12 TM0D4 PA4 PB4 X PAC4 PBC4 X PAWUE4 PAIM4 PBIM4 X M_BP4 S_BP4 CLK-MOD LCD_D4 X Bit 3 RTC WDTEN X BZL3 BZH3 ORMSK WDTOVFG TM1D3 TM1D11 TM0D3 PA3 PB3 X PAC3 PBC3 X PAWUE3 PAIM3 PBIM3 X M_BP3 S_BP3 LCD-CS1 LCD_D3 STB Bit 2 BZ_CLK WS2 X BZL2 BZH2 RTCMSK OR_FG TM1D2 TM1D10 TM0D2 PA2 PB2 X PAC2 PBC3 X PAWUE2 PAIM2 PBIM2 X M_BP2 S_BP2 LCD-CS0 LCD_D2 X Bit 1 MDUT WS1 X BZL1 BZH1 Bit 0 MGEN WS0 X BZL0 BZH0
HT9580
State on POR 0001 0000 0000 0111 uuuu uuuu 0000 0000 0000 0000 0000 1111 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uu11 1111 1111 1111 uuuu uu11 uu11 1111 1111 1111 uuuu uu11 uu00 0000 uu11 1111 1111 1111 uuuu uu11 0000 0000 0000 0000 0000 1101 uuuu uuuu uu0u uu01
TMR0_PR1 TMR0_PR0
TM1IMSK TM0IMSK TMR1EN TM1D1 TM1D9 TM0D1 PA1 PB1 PC1 PAC1 PBC1 PCC1 PAWUE1 PAIM1 PBIM1 PCIM1 M_BP1 S_BP1 LCD-A0 LCD_D1 RES TMR0EN TM1D0 TM1D8 TM0D0 PA0 PB0 PC0 PAC0 PBC0 PCC0 PAWUE0 PAIM0 PBIM0 PCIM0 M_BP0 S_BP0 LCD-WRB LCD_D0 ON
TM1OVFG TM0OVFG 0000 0000
TMR1CLK TMR0CLK TMR1EDG TMR0EDG
BP_MODM1 BP_MODM0 LCD-CHIP1 LCD-CHIP0
uuuu uuuu 0000 0000 uuuu u1uu 0uuu uuuu 0111 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
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April 28, 2000
Preliminary
HT9580 memory attribute table (I/O and data space)
Address 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH 000FH 0010H 0011H 0012H 0013H 0014H 0015H 0016H 0017H 0018H 0019H 001AH~ 002EH 002FH 0030H 0031H 0032H 0033H 0034H 0035H 0036H 0037H 0038H 0039H 003AH 003BH Register Name Config. WDT-TMR CLR WDT BZ-L BZ-H INT ctrl INT flag TMRC TMR1L TMR1H TMR0 PA data PB data PC data PAC PBC PCC PA WUE PA IM PB IM PC IM MROM-BP SRAM-BP LCD_CTRL LCD_CMD Decoder Control/ flag Decoder Configuration Memory D/A-L D/A-H Buffer Status SPI-CONFIG SPI-SPEED SPI-OUT3 SPI-OUT2 SPI-OUT1 SPI-OUT0 SPI-IN3 SPI-IN2 SPI-IN1 SPI-IN0 Bit 7 R/W X W R/W R/W 0 0 R/W R/W R/W R/W X R/W X X R/W X X X R/W X R/W R/W R/W R/W X Bit 6 R/W X W R/W R/W 0 R/W X R/W R/W R/W X R/W X X R/W X X X R/W X R/W R/W R/W R/W R/W Bit 5 R/W R/W W R/W R/W 0 R/W R/W R/W R/W R/W R/W R/W X R/W R/W X R/W R/W R/W X R/W R/W R/W R/W R Bit 4 R/W R/W W R/W R/W R/W R R/W R/W R/W R/W R/W R/W X R/W R/W X R/W R/W R/W X R/W R/W R/W R/W X Bit 3 R/W R/W W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W X R/W R/W X R/W R/W R/W X R/W R/W R/W R/W R Bit 2 R/W R/W W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W X R/W R/W X R/W R/W R/W X R/W R/W R/W R/W X Bit 1 R/W R/W W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit 0 R/W R/W W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
HT9580
State on POR 0001 0000 0000 0111 uuuu uuuu 0000 0000 0000 0000 0000 1111 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uu11 1111 1111 1111 uuuu uu11 uu00 0000 uu00 0000 0000 0000 uuuu uu00 0000 0000 0000 0000 0000 1101 uuuu uuuu uu0u uu01
R/W R/W X R R/W R/W R/W R/W R/W R/W R R R R
R/W R/W X X R/W R/W R/W R/W R/W R/W R R R R
R/W R/W X R R/W R/W R/W R/W R/W R/W R R R R
R/W R/W X R R R/W R/W R/W R/W R/W R R R R
R/W R/W X R R R/W R/W R/W R/W R/W R R R R
R/W R/W R/W R R/W R/W R/W R/W R/W R/W R R R R
R/W R/W R R R/W R/W R/W R/W R/W R/W R R R R
R/W R/W R R R/W R/W R/W R/W R/W R/W R R R R
uuuu uuuu 0000 0000 uuuu u1uu 0uuu uuuu 0111 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Note: R Read Only W Write Only R/W Read or Write X N/A
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April 28, 2000y
Preliminary
Configuration register
Address 0000H Register Name Config. Bit 7 HALT Bit 6 CLK_SEL Bit 5 OSC_MOD Bit 4 LPM Bit 3 RTC Bit 2 BZ_CLK Bit 1 MDUT Bit 0 MGEN
HT9580
State on POR 0001 0000
Oscillator configuration There are two clock source input pins on the chip, the main clock and the pager decoder input clock. The main clock is generated by an RC network. The system clock may be the OSC inp u t o r t he X 1 - c l oc k d ep end i ng o n b i t CLK_SEL. The pager decoder input clock comes from two external pins, X1 and X2. The frequency of the sub-clock will be double that of the X1, X2 input clock. The OSC1 main clock will be generated from an RC network that needs an external resistor (see Application Circuit). The system clock may be X1-clock, DF or RC clock. If no higher frequency (RC) is needed, the external resistor between OSC1 and OSC2 can be removed. The system clock can be switched by bit CLK_SEL. If CLK_SEL=0 (POR State), the system clock will be X1-clock. In other cases, with CLK_SEL=1, the OSC input clock will be the system clock. The clock switching function will assist software programmers to change the mC system clock within an adequate time if necessary. The
OSC1 M a in C lo c k OSC C o n tro l F re q u e n c y D o u b le r
OSC_MOD bit selects the OSC input clock to be either RC or DF. If OSC_MOD is set to low then the RC configuration is selected, otherwise the DF application is selected. The programmer should note that the condition of CLK_SEL, HALT and OSC_MOD assures that the system clock is working properly. It is recommended that the OSC clock source is either DF or RC. If DF and RC are necessary, it is required to switch the system clock to X1-clock before switching between DF and RC. Then switch the system clock back to the OSC input by using bit CLK_SEL if the switching action of DF and RC is complete. Before enter HALT mode, the system clock must select X1-clock. The HT9580 will generate two RTC frequencies, 1Hz and 2Hz respectively, determined by bit RTC. If the bit is logic low, the 1Hz RTC frequency will be selected, otherwise the 2Hz RTC frequency will be selected. The RTC counter is enabled/disabled by bit RTCEN and can be masked or not masked as determined by the bit RTCMSK of the interrupt control register
SST 1 0 - b it R ip p le C o u n te r X 1 - c lo c k X1
O SC_M O D 0:R C 1:D F
DF S u b - c lo c k H ALT
S S T C o n tro l
OSC In p u t
X 1 - c lo c k
C lo c k S e le c t
S y s te m 0 : X 1 - c lo c k 1 : O S C In p u t
C lo c k
CLK_SEL
1 H z & T im e O u t X 1 - c lo c k C o u n te r 2 H z & T im e O u t RTC T im e O u t
RTC
RTC block diagram
10 April 28, 2000
Preliminary
(0005H). If the RTC counter is enabled, the RTC counter will start to count. The RTC counter source clock is the X1-clock, so the X1 clock setting via by SPF12, SPF13 and SPF14 should be correct. In order to guarantee that the system clock has started and stabilized, the SST (System Start-up Timer) provides an extra delay of 1024 system clock pulse when the system is powered up. 1 RTC Select 2Hz as the RTC 0 Select 1Hz as the RTC
VSS Low p o w e r o s c illa to r fu n c tio n V
DD
HT9580
100kW 50kW
LPM (L o w
p o w e r m o d e c o n tr o l)
X2 50kW 100kW
HT9580
X1
The low power oscillator of the pager decoder input clock should be crystal type. The decoder subsystem low power oscillator, on the other hand, is of a crystal type which is designed with a power on start-up function to reduce the stabilization time of the oscillator. This start-up function is enabled by bit LPM which is initially set high at power on reset, and should be cleared to low so as to enable the low-power oscillator function. The oscillator configuration is running in the low power mode. The system clock oscillator can be enabled/disabled by the register bit, HALT. The system clock circuit is powered down, when the bit is set to high. On the other hand, the system clock WDT-TMR (Watchdog timer) register
Address 0001H 0002H Register Name WDT-TMR CLR WDT Bit 7 X X Bit 6 X X Bit 5 Bit 4
low power oscillator circuit is powered up, when the bit is low. When this bit is set high, the CPU is also stopped. When this bit is cleared low, the CPU core returns to its normal operation. After this is set HIGH by the software, it may also be cleared low when reset, interrupt (IRQ or NMI), RTC timeout, and port wake-up conditions are met. 0 System clock HALT enable 1 System clock powered down
The WDT is a 16-bit counter and sourced by the
Bit 3 WDTEN X
Bit 2 WS2 X
Bit 1 WS1 X
Bit 0 WS0 X
State on POR 0000 0011 uuuu uuuu
TMR0_PR1 TMR0_PR0 X X
sub-clock divided by 8. The counter is segmented as a 9-bit prescaler and a 7-bit user programmable counter. The input clock is first divided by 512 (9-stage) to get the nominal time-out period. The output of the 9-bit pre-scaler can then be divided by a 7-bit programmable counter to generate the longer watchdog time-out depending on the users requirements. The 7-bit programmable counter is controlled by 3 register bits, WS0~2. The watchdog timer is enabled/disabled by a control bit WDTEN. To prevent the overflow of this watchdog timer, a clear-WDT operation should
be executed before the timer overflows. The clear-WDT operation is to write any number to the register, CLRWDT (0002H). When the watchdog timer overflows (checked by bit 3 of 0006H WDTOVFG), the program counter is set to FFFC H and FFFD H to read the program start vector. The definitions of the control bits are listed below. 1 Enable the WDTEN watchdog timer 0 Disable the watchdog timer
11
April 28, 2000
Preliminary
The WDT 7-bit counter is programmed by bits WS0~WS2. The division ratio for the counter is listed in the table. WS2 0 0 0 0 1 1 1 1 WS1 0 0 1 1 0 0 1 1 WS0 0 1 0 1 0 1 0 1 Division Ratio 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 0 0 1 1 0 1 0 1
HT9580
The other pair TMR0_PR0 and TMR0_PR1 are used to select the prescaler ratio for timer0. The definition is shown in the table. TMR0_PR1 TMR0_PR0 TMR0 Prescaler Ratio 1/4 1/8 1/16 1/32
X 1 - c lo c k
1 /8
9 - b it P r e s c a le r
7 - b it C o u n te r
W S0~2
8 to 1 M U X
W D T tim e - o u t
Buzzer generator registers
Address 0003H 0004H Register Name BZ-L BZ-H Bit 7 BZL7 BZH7 Bit 6 BZL6 BZH6 Bit 5 BZL5 BZH5 Bit 4 BZL4 BZH4 Bit 3 BZL3 BZH3 Bit 2 BZL2 BZH2 Bit 1 BZL1 BZH1 Bit 0 BZL0 BZH0 State on POR 0000 0000 0000 0000
The buzzer generator is composed of a 16-bit PFD counter and a duty cycle control. The counter value is set by two registers, namely BZ-H and BZ-L. The source for this generator may be the system clock or the X1-clock. The buzzer generator is enabled/disabled by the register bit MGEN in the configuration register(0000H). When this bit is set high, the buzzer generator is activated. There is another bit in the configuration register(0000H) which controls the buzzer output volume, bit MDUT. If the bit is logic high, the output of the BZ will be modulated by the X1-clock. The
clock source of the buzzer is selected by bit BZ_CLK. When BZ_CLK=0, the clock source is the system clock. On the other hand, when BZ_CLK=1, the value of the selector will be the X1-clock. The truth table for enabling/disabling the buzzer generator is shown in the table. 1 MGEN 0 Enable the Disable the buzzer generator buzzer generator
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April 28, 2000
Preliminary
When BZ-L and BZ-H are all 00H, the tone generator is disabled and BZ is high. The value of t h e f r eq uenc y d i v i d er, r a ng es fr o m 2 (BZ-L=01H, BZ-H=00H)~65536 (BZ-L=FFH, BZ-H=FFH). Writing to BZ-L only writes the data into a low byte buffer, while writing to BZ-H will write the high byte data and the contents of the low byte buffer into the PFD counter. When the buzzer generator is disabled by clearing the MGEN bit in the configuration register (0000H), the BZ pin remains at its last state. If the BZ pin is low, the BZ transistor in
BZ_CLK=0 BZ_CLK=1 1 6 - b it P F D C o u n te r 2 PW M M o d u la to r BZ
HT9580
the application circuits is always active. Therefore it is recommended that both BZ-L and BZ-H be cleared and that the MGEN bit in the configuration register (0000H) also be cleared, when it is desired to disable or stop the buzzer. The output of the 16-bit PFD counter is divided by 2 to generate a BZ output with or without modulation. For example, if the desired output of BZ is 1.6kHz with modulation and the frequency source is X1-clock (76.8kHz), then the value of 16-bit PFD counter is set to BZ-L=17H, BZ-H=00H and MDUT is set high.
X 1 - c lo c k
S y s te m
C lo c k
X 1 - c lo c k
BZ_CLK
M DUT=0 M DUT=1
MGEN
MDUT
Interrupt registers
Address 0005H 0006H Register Name INT ctrl INT flag Bit 7 0 0 Bit 6 0 RTC_FG Bit 5 0 DR_FG Bit 4 RTCEN BF_FG Bit 3 ORMSK WDTOVFG Bit 2 RTCMSK OR_FG Bit 1 TM1IMSK TM1OVFG Bit 0 TM0IMSK TM0OVFG State on POR 0000 1111 0000 0000
There are two interrupts for the HT9580: a Non-Mask Interrupt (NMI) and a generic interrupt request (IRQ). The data ready interrupt and battery fail interrupt share the NMI call location. Which interrupt occurred can be determined by checking bit BF_FG and the data ready interrupt bit DR_FG or SPI complete flag SPIFG (in SPI-CONFIG register). DR_FG is the data ready interrupt indication bit. When a valid call is detected, data begins to transfer. Either one call is terminated or a message buffer is full or one batch is over but the message is not terminated, the data ready interrupt will occur and DR_FG is set high. The DR_FG bit should be cleared low by the mC software after a data ready condition has occurred.
13
A battery fail condition is triggered by a high to low transition on pin BAF and will set the battery fail interrupt request flag BF_FG to logic high. For details, refer to the POCSAG Decoder section. The sources for the IRQ are timer 0 overflow, timer 1 overflow, out-of-range status changes and RTC time out. The four interrupt sources all could be masked, but the four corresponding interrupt flags will still be set when the interrupt conditions are met. All the four flags are readable/writeable. When an interrupt condition is met, a flag will be set. If an interrupt routine is performed, the software should check which flag is set to high then determine what kind of interrupt source occurred. The WDTOVFG is the flag for the watchdog
April 28, 2000
Preliminary
timer overflow and RTC_FG is an indicator for the RTC time out interrupt request flag. The OR_FG will be set high when an out-of-range status from low to high or high to low transition occurrs. Those flags such as TM0OVFG, TM1OVFG, BF_FG, DR_FG, OR_FG and RTC_FG should be cleared by the software after they are activated. 1 RTCEN RTCMSK TM0IMSK RTC counter is enabled RTC interrupt is masked 0 RTC counter is disabled RTC interrupt is not masked 1 TM0OVFG TM1OVFG Timer 0 overflows Timer 1 overflows
HT9580
0 No timer 0 overflow No timer 1 overflow No watchdog timer overflow No battery fail request No data ready request No out-of-range request No RTC interrupt request
Watchdog WDTOVFG timer has overflown BF_FG DR_FG OR_FG RTC_FG Battery fail request Data ready request Out-of-range request RTC interrupt request
Timer 0 overflow Timer0overflow interrupt is interruptisnot masked masked Timer 1 overflow interrupt is masked Out-of-range interrupt is masked Timer 1 overflow interrupt is not masked Out-of-range interrupt is not masked
D a ta R e a d y S P IR eqst B a tte r y F a il T M 0 /1 IM S K T M 0 /1 O V F G RTC_FG RTCM SK O R_FG ORMSK
TM1IMSK
ORMSK
NMI
M 6502 C o re
IR Q
Block diagram of NMI and IRQ
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April 28, 2000
Preliminary
tim e r 0 o v e r flo w S tim e r 1 o v e r flo w S tim e r 0 o v e r flo w S tim e r 1 o v e r flo w S tim e r 0 o v e r flo w S tim e r 0 o v e r flo w S tim e
HT9580
IR Q M asked by TM 0O VFG T M 0 IM S K M asked by T M 0 IM S K M asked by TM 1O VFG
T M 1 IM S K C le a r e d b y s o ftw a r e TM 0O VFG C le a r e d b y s o ftw a r e TM 1O VFG C le a r e d b y s o ftw a r e C le a r e d b y s o ftw a r e C le a r e d b y s o ftw a r e
Timer0 and Timer1 timing diagram Reset conditions The HT9580 will reset the whole chip when the following conditions are met:
* Power On * The external RESET pin is held low for at
least 1 ms
* The WDT overflows
The input is used to reset the mC. Reset must be held low at least 1 ms after VDD reaches operating voltage from a power down. A positive
transition on the chip reset will then cause an initialization sequence to begin. After the system is operating, a low on this line of at least 1 ms in duration will cause mC activity. When a positive edge is detected, there is an initialization sequence lasting 8-clock cycles. Then the interrupt mask flag is set, the decimal mode is cleared and the program counter is loaded with the restart vector from locations FFFC (low byte) and FFFD (high byte). This is the start location for program control. This input should be high during normal operation.
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April 28, 2000
Preliminary
5000H
HT9580
P ro g ra m
ROM
S pace
FFFAH FFFBH FFFCH FFFDH FFFEH FFFFH
D a ta R e a d y & B a tte r y F a il S e r v ic e R o u tin e V e c to r L o w B y te D a ta R e a d y & B a tte r y F a il S e r v ic e R o u tin e V e c to r H ig h B y te P ro g ra m P ro g ra m IR Q IR Q R e s e t V e c to r L o w B y te
V
DD
RESET
R e s e t V e c to r H ig h B y te B y te
S e r v ic e R o u tin e V e c to r L o w
HT9580
S e r v ic e R o u tin e V e c to r H ig h B y te
RESET
In te r n a l P u ll- u p
P o w e r O n D e te c to r
S y s te m
C lo c k
1 0 - b it R ip p le C o u n te r
C h ip R e s e t G e n e r a to r
W D T O v e r flo w
VDD RESET OSC T im e - O u t C h ip R e s e t
1 0 2 4 C lo c k C y c le s
VDD 8 C lo c k C y c le s RESET W D T T im e - O u t C h ip R e s e t
Power on reset timing
RESET active and WDT time-out
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April 28, 2000
Preliminary
Timer registers
Address 0007H 0008H 0009H 000AH Register Name TMRC TMR1L TMR1H TMR0 Bit 7 TMR1MOD TM1D7 TM1D15 TM0D7 Bit 6 X TM1D6 TM1D14 TM0D6 Bit 5 TMR1CLK TM1D5 TM1D13 TM0D5 Bit 4 TMR0CLK TM1D4 TM1D12 TM0D4 Bit 3 TMR1EDG TM1D3 TM1D11 TM0D3 Bit 2 TMR0EDG TM1D2 TM1D10 TM0D2 Bit 1 TMR1EN TM1D1 TM1D9 TM0D1 Bit 0 TMR0EN TM1D0 TM1D8 TM0D0
HT9580
State on POR 0u00 0000 uuuu uuuu uuuu uuuu uuuu uuuu
In addition to the watchdog timer, the HT9580 provides two timers: an 8-bit timer (timer 0) and one 16-bit timer (timer 1). Those two timers are controlled and configured by the register TMRC. Both timers are programmable up-count counters whose clocks may be derived from the X1-clock (32.768kHz, 76.8kHz or 153.6kHz). To program the timers, TMR0, TMR1L, and TMR1H should be written with a start value. When the timers are enabled, they will count-up from the start value. If the timers overflow, corresponding interrupts will be generated. When the timers are disabled, the counter contents will not be reset. To reset the counter contents, the software should write the start value again. Since timer1 is a 16-bit counter, it is important to note the method of writing data to both TMR1L and TMR1H. Writing to TMR1L only writes the data into a low byte buffer, while writing to TMR1H will simultaneously write the high byte data and the contents of the low byte Labels (TMRC0 and TMRC1) TMR0EN, TMR1EN TMR0EDG, TMR1EDG TMR0CLK TMR1CLK TMR1MOD Bits 0 1 2 3 4 5 7
buffer into the Timer Counter preload register (16-bit). Note that the Timer counter preload register contents are changed by a TMR1H write operation while writing to TMR1L does not change the contents of the preload register. Reading TMR1H will also latch the contents of TMR1L into the byte buffer to avoid false timing problem. Reading TMR1L returns the contents of the low byte buffer. In other words, the low byte of the timer counter cannot be read directly. It must first read TMR1H to latch the low byte contents of the timer counter into the buffer. TMRC is the timer counter control register, which defines the timer counter options. The timer1 clock source can be selected from either the internal clock or an external input clock by bit TMR1MOD of the TMRC register. The timer0/timer1 can also select its clock source by bits TMR0CLK/TMR1CLK. TMRC as shown in the table. Function
Enable/disable timer counting (0=disable; 1=enable) Define the TMR0 and TMR1 active edge (0=active on low to high; 1=active on high to low) Select TMR0 clock source (0=X1-clock; 1=OSC1 input clock/system clock) Select TMR1 clock source if internal clock input is selected (0=X1-clock; 1=OSC1 input clock/system clock) Define the TMR1 operation mode (0=internal clock input; 1=external clock input)
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April 28, 2000
Preliminary
S y s te m C lo c k 0 1 TM R0CLK D a ta B u s T im e r C o u n te r P r e lo a d R e g is te r R e lo a d
HT9580
X 1 - C lo c k
P r e s c a le r TM R0_PR 1 TM R0_PR 0
E d g e S e le c t TM R0EDG
T im e r 0 C o u n te r ( 8 - b it) TM R0EN
O v e r flo w T o In te rru p t
Timer 0 block diagram
S y s te m
C lo c k 0
1
TM R1CLK D a ta B u s T im e r /e v e n t C o u n te r P r e lo a d R e g is te r 0 E d g e S e le c t 1 TM R1M O D TM R1EDG T im e r 1 C o u n te r ( 1 6 - b it) TM R1EN R e lo a d
X 1 - C lo c k
TM R1
O v e r flo w T o In te rru p t
Timer 1 block diagram
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April 28, 2000
Preliminary
I/O port configuration registers
Address 000BH 000CH 000DH 000EH 000FH 0010H 0011H 0012H 0013H 0014H Register Name PA data PB data PC data PAC PBC PCC PA WUE PA IM PB IM PC IM Bit 7 X PB7 X X PBC7 X X X PBIM7 X Bit 6 X PB6 X X PBC6 X X X PBIM6 X Bit 5 PA5 PB5 X PAC5 PBC5 X PAWUE5 PAIM5 PBIM5 X Bit 4 PA4 PB4 X PAC4 PBC4 X PAWUE4 PAIM4 PBIM4 X Bit 3 PA3 PB3 X PAC3 PBC3 X PAWUE3 PAIM3 PBIM3 X Bit 2 PA2 PB2 X PAC2 PBC2 X PAWUE2 PAIM2 PBIM2 X Bit 1 PA1 PB1 PC1 PAC1 PBC1 PCC1 PAWUE1 PAIM1 PBIM1 PCIM1 Bit 0 PA0 PB0 PC0 PAC0 PBC0 PCC0 PAWUE0 PAIM0 PBIM0 PCIM0
HT9580
State on POR uu11 1111 1111 1111 uuuu uu11 uu11 1111 1111 1111 uuuu uu11 uu00 0000 uu11 1111 1111 1111 uuuu uu11
The HT9580 has three general purpose I/O ports. The I/O cell structures are configurable. Details are shown in the table. Port A Port A is a general-purpose I/O port. The PAC register controls the data directions for port A. When set as input data type, this port has wake-up capability and the input cell structures are schmitt trigger types. While in a HALT condition, a falling edge signal on Port A can wake-up the mC. In addition, the input cell structures can be configured as pull-high or non-pull-high. When set as an output data type, the output structures are CMOS outputs. 1 PA PAC The pin output logic high As input pin 0 The pin output logic low As output pin The pin has no wake-up capability CMOS input structure without pull-high resistor
Port B Port B is a general-purpose I/O port controlled by the PBC register. The PBIM register controls the input cell structures: normal CMOS inputs or CMOS inputs with pull-high resistors. 1 PB PBC PBIM Pin output logic high Input pin 0 Pin output logic low Output pin
CMOS input CMOS input structure with structure without pull-high pull-high resistor resistor
Port C This is a general-purpose I/O port contolled by the PCC register. The PCIM register controls the input cell structures: normal CMOS inputs or CMOS inputs with pull-high resistors. 1 PC PCC PCIM The pin output logic high As input pin CMOS input structure with pull-high resistor 0 The pin output logic low As output pin CMOS input structure without pull-high resistor
The pin has PAWUE wake-up capability PAIM CMOS input structure with pull-high resistor
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April 28, 2000
Preliminary
M P A D a ta U X EN V
DD
HT9580
P u ll- u p R e s is to r
PAC P A IM O ne Shot C ir c u it
PAW UE
To CPU
I/O structure of port A Mask ROM (Character ROM) bank point register
Address 0015H Register Name Bit 7 Bit 6 Bit 5 M_BP5 Bit 4 M_BP4 Bit 3 M_BP3 Bit 2 M_BP2 Bit 1 M_BP1 Bit 0 M_BP0 State on POR 0000 0000
MROM-BP BP_MODM1 BP_MODM0
The Mask ROM bank point register can switch between the internal 2 Mbits Mask ROM or an external up to 2 Mbits Mask ROM space. The selection table is based on the following table. The space size of each Mask ROM bank is 8 Kbytes. The bits BP_MODM1 and BP_MODM0 define whether internal or external Mask ROM devices are used. (BP_MODM1, BP_MODM0)=(0, 1), sel e c t s t he i nter na l M a s k RO M d e v i c e .
BP_MODM1 BP_MODM0 M_BP5 0 0 0 0 0 0 0 1 1 1 0 1 1 1 1 1 1 0 0 0 0 1 1 1 0 1 0 1 0 1 1 0 1 1 0 1 0 1 0 1 0 X 0 M_BP4 X 0 M_BP3 X 0 1 0 1 0 M_BP2 X 0
(BP_MODM1, BP_MODM0)=(1, 0), selects the external Mask ROM device. The internal Mask ROM can switch from bank 0 to bank 31 and the external Mask ROM can switch from bank 0 to bnak 31 by software programming. In addition, the address range of the internal/external Mask ROMwillallrangefrom1000Hto2FFFH. The Mask ROM bank point register selection table is shown in the table.
M_BP1 M_BP0 BP Value X 0 X 0 X 0 1 0 31 32 1 0 63 0 1 31 Reserved Internal 2 Mbits Mask ROM (low 8 Kbytes) Memory Area
Internal 2 Mbits Mask ROM (High 8 Kbytes) Reserved Reserved Reserved External 2 Mbits Mask ROM (low 8 Kbytes) External 2 Mbits Mask ROM (High 8 Kbytes)
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April 28, 2000
Preliminary
If the internal 2 Mbits mask ROM is placed as shown in the figure and the software programmer obtains a start address from CNS (Taiwan) code or a GB (China) code, A0~A17. The following steps will map from the start address to the bank point register, then the hardware address decode circuit will point to the real 2 Mbits space. (If the internal mask ROM is selected.)
* Step 1
00000H C N S P a tte rn (G B P a tte rn ) (A 1 8 = "0 ") 3FFFFH 40000H R e s e rv e d (A 1 8 = "1 ") 7FFFFH
HT9580
The formula obtains A0~A18 from the received GB or CNS code. If it is in the lower 2 Mbits space, A18=0. Otherwise, A18=1 if it is in reserved space.
* Step 2
* Step 5
Set (BP_MODM1, BP_MODM0)=(0, 1)
* Step 3
The following example will load 32 bytes continuous (one Chinese word) pattern from the internal mask ROM and store them to the start address $C3C2C1C0 H (if absolute index addressing mode is used). LDX #00H LDY #00H READ: LDA $B3B2B1B0, X STA $C3C2C1C0, Y INX INY CPX #20H BNZ READ
Assign correct M_BP0~M_BP5 as shown: A13(R)M_BP0 A14(R)M_BP1 A15(R)M_BP2 A16(R)M_BP3 A17(R)M_BP4 A18(R)M_BP5 (the bit will be 0 at this condition) * Step 4 Adding $1000 H to A12~A0 to get new HEX value $B3B2B1B0 H.

0 0 0 0 0
0 0
0 1 R A13
A12 0 R A12
A11 0 A11
A10 0 A10
A9 0 A9
A8 0 A8
A7 0 A7
A6 0 A6
A5 0 A5
A4 0 A4
A3 0 A3
A2 0 A2
A1 0 A1
A0 A0
B
3
(0 ,0 ,R A 1 3 ,R A 1 2 )
B
2
(A 1 1 ,A 1 0 ,A 9 ,A 8 )
B
1
(A 7 ,A 6 ,A 5 ,A 4 )
B
0
(A 3 ,A 2 ,A 1 ,A 0 )
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April 28, 2000
Preliminary
SRAM bank point register
Address 0016H Register Name SRAM-BP Bit 7 Bit 6 Bit 5 S_BP5 Bit 4 S_BP4 Bit 3 S_BP3 Bit 2 S_BP2 Bit 1 S_BP1 Bit 0 S_BP0
HT9580
State on POR 0000 0000
BP_MODS1 BP_MODS0
The SRAM bank point register can switch to either external 256 Kbytes or internal 32 Kbytes SRAM space. The selection table is based on the following table. The space size of each SRAM bank is 8 Kbytes. Bits BP_MODS1 and BP_MODS0 define whether internal or external SRAM devices are used. (BP_MODS1, BP_MODS0)=(0, 1), is for internal SRAM deBP_MODS1 BP_MODS0 0 0 0 0 0 0 0 1 1 1 0 1 1 1 1 1 1 0 0 0 0 1 1 1 0 1 0 1 0 1 1 0 0 0 0 0 0 1 0 1 0 S_BP5 X 0 S_BP4 X 0 S_BP3 X 0 0 1 1 0 S_BP2 X 0 X 0
vices. (BP_MODS1, BP_MODS0)=(1, 0), is for external SRAM devices. The internal SRAM would switch from bank 0 to bank 3 and the external SRAM would switch from bank 0 to bank 31 by software programming. In addition, the address range of the internal/external SRAM will all range from 3000H to 4FFFH.
S_BP1 S_BP0 X 0 BP Value X 0 1 0 3 4 1 0 63 0 1 31 Reserved Internal 32 Kbits SRAM (Low 8 Kbytes) Internal 32 Kbits SRAM (High 8 Kbytes) Reserved Reserved Reserved External 256 Kbits SRAM (Low 8 Kbytes) External 256 Kbits SRAM (High 8 Kbytes) Memory Area
LCD control and data register
Address 0017H 0018H Register Name Bit 7 Bit 6 LCD-CHIP0 LCD_D6 Bit 5 LCD-CLK LCD_D5 Bit 4 CLK-MOD LCD_D4 Bit 3 LCD-CS1 LCD_D3 Bit 2 LCD-CS0 LCD_D2 Bit 1 LCD-A0 LCD_D1 Bit 0 LCD-WRB LCD_D0 State on POR 0000 1101 uuuu uuuu
LCD_CTRL LCD-CHIP1 LCD_CMD LCD_D7
The LCD control and command registers are used for LCD driver interface. There are three kinds of LCD driver chips available for the HT9580. These LCD drivers are SED15X(KSX) series, Motorola LCD driver chip MC141X series and HD66410 respectively according to the following LCD-CHIP0 and LCD-CHIP1 bit table settings. The combination of the LCD_CMD and LCD-CTRL registers can control the SED15X(KSX), MC141X series or HD66410 LCD drivers. Bits LCD-CS0/1 of the
LCD-CTRL register corresponds to the chip select pin of the LCD driver. The bit LCD-CS0 is used to control the master LCD driver chip while LCD-CS1 is for the slave LCD driver chip. Both bits are active low. The bit CLK_MOD is used to enable or disable the pin out of LCD_CL. If the bit is set low, the clock output of pin LCD_CL will be disabled, otherwise the LCD_CL clock will be set according to the following Truth Table.
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April 28, 2000
Preliminary
LCD-CHIP0 and LCD-CHIP1 Truth Table LCD-CHIP0=0 LCD-CHIP1=0 LCD-CHIP1=1 LCD-CHIP0=1
HT9580
SED15X(KSX) series LCD driver is MC141X series LCD driver is selected selected HD66410 LCD driver is selected N/A
LCD_CL Truth Table LCD-CHIP0=0 LCD-CHIP1=0 LCD-CHIP1=1 LCD_CL: 2 kHz output LCD_CL: 10.9kHz output LCD-CHIP0=1 LCD_CL: If LCD-CLK=0, 32 kHz output If LCD-CLK=1, X1-clock output N/A
The following is a comparison table of the HT9580 pin description between the SED15X (KSX) series and the MC141X series LCD driver. HT9580 (Pin) SED15X(KSX) Series Data/command select input. A0=0: Display control data on D/C D0~D7 A0=1: Display data on D0~D7 MC141X Series This input pin acknowledges valid data on D0~D7. If high then D0~D7 contains display data, if low D0~D7 containscommanddata.
LCD_A0
A0
LCD_CS0 CS (Master)
When high, enables the Active low chip select input. CE (Master) control pins on the driver. (Master) (Master) Active low chip select input. CE (Slave) (Slave) 8-bit, tristate, bidirectional I/O D0~D7 bus. Enable clock input CS When high, enables the control pins on the driver. (Slave) Bidirectional bus for data/command transfer. This pin is normal low clock input. Data on D0~D7 is latched at the falling edge of CS. To read the display data RAM or the internal status, pull this pin high. The pin low indicates a write operation. Oscillator input for external clock is used. (32kHz or X1-clock output from HT9580 as determined by the LCD-CLK).
LCD_CS1 CS (Slave) D0~D7 D0~D7
LCD_E
E
LCD_RW R/W
Read/write input
R/W
LCD_CL
CL
External clock input. (2kHz output from HT9580)
OSC2
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April 28, 2000
Preliminary
LCD LCD_A0 L C D _ C S 0 (M a s te r) L C D _ C S 1 ( S la v e ) D0~D7 2 15~8 7 E 6 4 R /W CL 3 5 A0 C S (M a s te r) C S ( S la v e ) D0~D7 D r iv e r M a s te r S la v e
HT9580
HT9580
LCD_E LCD_RW LCD_CL
S E D 1 5 X (K S X )
T h e a p p lic a tio n c ir c u it w h e n b it " L C D - C H IP 1 " = 0
a n d "L C D -C H IP 0 " = 0
L C D D r iv e r LCD_A0 L C D _ C S 0 (M a s te r) L C D _ C S 1 ( S la v e ) 2 15~8 7 6 4 3 5 D /C C E (M a s te r) C E ( S la v e ) D0~D7 CS R /W OSC2 M a s te r S la v e
HT9580
D0~D7 LCD_E LCD_RW LCD_CL
M C 141X
T h e a p p lic a tio n c ir c u it w h e n b it " L C D - C H IP 1 " = 0
a n d "L C D -C H IP 0 " = 1
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April 28, 2000
Preliminary
LCD LCD_A0 L C D _ C S 0 (M a s te r) L C D _ C S 1 ( S la v e ) 2 15~8 7 6 4 3 5 RS C S (M a s te r) C S ( S la v e ) D0~D7 RD WR CR D r iv e r M a s te r S la v e
HT9580
HT9580
D0~D7 LCD_E LCD_RW LCD_CL
HD66410
T h e a p p lic a tio n c ir c u it w h e n b it " L C D - C H IP 1 " = 1
LCD Driver Chip Selection Application
a n d "L C D -C H IP 0 " = 0
Note
LCD-CHIP0="0" LCD-CHIP1="0"
SEDX(EPSON) series LCD driver at 68 family MPU appli- RESET is low active cation mode. KSX(SAMSUNG) series LCD Pin options set as 68 family driver at 68 family MPU appliMPU application mode. cation mode. MC14X(MOTOROLA) series LCD driver. HD66410(HITACHI) series LCD driver.
LCD-CHIP0="1" LCD-CHIP1="0"
LCD-CHIP0="0" LCD-CHIP1="1"
SEDX(EPSON) series LCD d r i v e r a t 8 0 f a m i l y M P U RESET is high active application mode. KSX(SAMSUNG) series LCD Pin options set as 80 family driver at 80 family MPU appliMPU application mode. cation.
LCD-CHIP0="1" LCD-CHIP1="1"
N/A
Power down operation - HALT The HALT mode is initiated by setting the configuration register bit HALT high and results in the following ... The system clock turns off, the low power pager sub-clock, LCD driver, pager decoder and RTC all keep running.
25
The contents of the on-chip RAM and of the register remain unchanged. As the WDT and the WDT prescaler depend on software control, the WDT will continue to count when the HALT bit is set high. All the I/O ports remain in their original status.
April 28, 2000
Preliminary
D/A registers
Address 002FH 0030H Register Name D/A-L D/A-H Bit 7 DA7 X Bit 6 DA6 X Bit 5 DA5 X Bit 4 DA4 X Bit 3 DA3 X Bit 2 DA2 D/A_PD Bit 1 DA1 RSSI Bit 0 DA0 BAT
HT9580
State on POR 0000 0000 uuuu u1uu
The system can quit the HALT mode by an external reset, an interrupt, an external falling edge signal on port A or an RTC time out. The HT9580 has one internal 8-bit D/A converter which can measure the battery voltage and the RSSI input signal from the IF of the RF circuit. The DA0~DA7 is the digital input of the D/A converter and the analog outputs to the pin named DA_OUT. Bit BAT of the DA-H register (0030H) is the output of the comparator. Its input at the - terminal is from the D/A output and the + terminal comes from the input pin
BAF. The bit RSSI of DA-H register (0030H) is the output of another comparator. Its input at - terminal is from the D/A output and + terminal comes from the input pin RSSI. The software can detect the battery voltage and the RSSI signal by writing to the bits DA0 ~DA7 (002FH) and reading the bits BAT, RSSI (0030H). Bit D/A_PD is used for the D/A power down control. If this bit is logic high, the D/A will be in the power down mode. Otherwise, the D/A is in the normal condition. For details see the following figure.
RSSI RSSI
V
DD
BAT D /A _ P D VDD (D /A ) DA7 DA6 VSS DA5 DA4 DA3 DA2 DA1 DA0 2R R R R R R R R 2R 2R 2R 2R 2R 2R 2R 2R
BAT
D A_O U T
T h e c o n fig u r a tio n o f th e 8 - b it D /A c o n v e r te r a n d p o w e r d o w n c o n tr o l
26
April 28, 2000
Preliminary
Buffer status register
Address 0031H Register Name Buffer Status Bit 7 MSG_END Bit 6 X Bit 5 count_5 Bit 4 count_4 Bit 3 count_3 Bit 2 count_2 Bit 1 count_1 Bit 0 count_0
HT9580
State on POR 0uuu uuuu
The buffer status register will relay to the mC the status of the message buffer when the data ready request interrupt occurred. The MSG_END bit will be set high when the data (including address codeword and message codeword) is at the end of this data ready interrupt call. The valid data length of the message buffer is determined by bit count_0 to count_5. If MSG_END is low, the data length is more
than 46 or data is not at the end, the mC should wait for the next data ready interrupt until the bit MSG_END is set high. Example 1: if the data read from 0031H is 95H when a new data ready interrupt occurred, it means the total data length is 21 including the address codeword in this call and the message is terminated (bit MSG_END =1). The figure below illustrates example 1.
M e s s a g e B u ffe r 0040H 0041H 0042H A d d re s s C o d e w o rd M e s s a g e C o d e w o rd 1 M e s s a g e C o d e w o rd 2
0053H 0054H 0055H
M e s s a g e C o d e w o rd 1 9 M e s s a g e C o d e w o rd 2 0 N /A
006DH
N /A
B it7 B it6 B it5 B it4 B it3 B it2 B it1 B it0 1 0 0 1 0 1 0 1 0031H
Example 1
27
April 28, 2000
Preliminary
Example 2: if the data read from 0031H is 2EH when a new data ready interrupt occurred, that means the data length of this call is more than 46 and the next data ready interrupt will occur. If the next interrupt occurs and the contents of 0031H is 85H, the result are
M e s s a g e B u ffe r 0040H 0041H 0042H A d d re s s C o d e w o rd M e s s a g e C o d e w o rd 1 M e s s a g e C o d e w o rd 2 0040H 0041H 0042H 0043H 0044H 0045H
HT9580
shown in the following figure. The programmer should note that the information on the message buffer must be read out before the next continuous codeword arrives. Otherwise the data on the message will be overwritten.
M e s s a g e B u ffe r M e s s a g e C o d e w o rd 4 6 M e s s a g e C o d e w o rd 4 7 M e s s a g e C o d e w o rd 4 8 M e s s a g e C o d e w o rd 4 9 M e s s a g e C o d e w o rd 5 0 N /A
006CH 006DH
M e s s a g e C o d e w o rd 4 4 M e s s a g e C o d e w o rd 4 5 006DH N /A
B it7 B it6 B it5 B it4 B it3 B it2 B it1 B it0 0 0 1 0 1 1 1 0 0031H
B it7 B it6 B it5 B it4 B it3 B it2 B it1 B it0 1 0 0 0 0 1 0 1 0031H
1 s t D a ta R e a d y In te rru p t
2 n d D a ta R e a d y In te rru p t
Example 2 The data ready interrupt will generate when message is terminated, synchronization code
POCSAG DATA S tru c tu re DI NMI DR_FG M e s s a g e B u ffe r (4 6 b y te s ) V a lid D a ta F ra m e 5 F ra m e 6 F ra m e 7
word is received or buffer is full. The following figure will show the typical operation.
S ync F ra m e 0 F ra m e 1 F ra m e 2
The timing chart of message buffer
28
April 28, 2000
Preliminary
SPI configure register
Address 0032H Register Name SPI-CONFIG Bit7 S/M Bit6 LEN1 Bit5 LEN0 Bit4 REQST Bit3 SPIFG Bit2 CLK_EDG Bit1 SPI_EN Bit0 START
HT9580
State on POR 0111 1000
* S/M: Slave/master mode selection
* CLK_EDG: Data sampling edge
When S/M is "0", HT9580 is in the master mode. Otherwise, HT9580 is in the slave mode. 0 S/M Master mode (SCK is output) 1 Slave mode (SCK is input)
The CLK_EDG will determine the valid MISO and MOSI sampling edge of SCK clock. 0 CLK_EDG Rising edge 1 Falling edge
* SPI_EN: The SPI enable
* LEN0, LEN1: Data length
0 When the SPI circuit is disabled, the SPI_EN POCSAG decoder I/O pins will be enabled
1 The SPI circuit and SPI I/O pins will be enabled
The LEN0 and LEN1 will determine the data length between exchange. LEN1 0 0 1 1 LEN0 0 1 0 1 Data Length (Bit) 4 8 16 32
* START: The data exchange start or not
0 START No data exchange
1 Data exchange start
* REQST: SPI request (read only)
When FLEXTM decoder wants to exchange data with HT9580, the REQST will have low pulse. 0 (clear): Data transfer to external device has been completed. 1 (set): No valid completion of data transfer. The bit is cleared by hardware and set by software.
* SPIFG: SPI complete flag
When the bit is set by software, the SPI data exchange will start. After the first bit data exchange is completed, the START bit will clear to low again by hardware.
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April 28, 2000
Preliminary
SPI SPEED register (write only)
Address 0033H Register Name SPI-SPEED Bit7 SP7 Bit6 SP6 Bit5 SP5 Bit4 SP4 Bit3 SP3 Bit2 SP2 Bit1 SP1 Bit0 SP0
HT9580
State on POR 0000 0000
The register will determine the SCK clock frequency of SPI. When SPEED register are 00H, the SCK clock output is high. The value of the frequency divider, ranging from 1 (SPEED=01H)~255 (SPEED=FFH). If SPEED=00H, the SCK output will be disabled.
X 1 - c lo c k 8 - b it S P E E D C o u n te r S P I C o n tro l SPI SCK
SPI output buffer register (write only)
Address 0034H 0035H 0036H 0037H Register Name SPI-OUT3 SPI-OUT2 SPI-OUT1 SPI-OUT0 Bit7 D7 D7 D7 D7 Bit6 D6 D6 D6 D6 Bit5 D5 D5 D5 D5 Bit4 D4 D4 D4 D4 Bit3 D3 D3 D3 D3 Bit2 D2 D2 D2 D2 Bit1 D1 D1 D1 D1 Bit0 D0 D0 D0 D0 State on POR 0000 0000 0000 0000 0000 0000 0000 0000
The SPI-OUT3~0 are used when transmitting data on the serial bus. Only valid data write to the register SPI-OUT3~0 and "START" initiating will begin the SPI data transmission from HT9580 to FLEXTM decoder. After completion of the 4-byte data transfer, the "SPIFG" status bit will be set and the internal signal REQST will generate a falling edge signal for NMI. The bit7 of SPI-OUT3 is MSB and bit0 of SPI-OUT0 is LSB.
S P IF G
REQST (N M I) REQST ( r e g is te r ) START ( r e g is te r ) SCK MOSI H T9580) M IS O d e c o d e r) S P I-O U T 3 ~ 0 MSB MSB 2 2 1 LSB L o g ic H ig h
(fro m (fro m
S P I-IN 3 ~ 0
1
LSB
S S (to d e c o d e r) (fro m SRDY d e c o d e r)
S P I p a c k e t e x c h a n g e in itia te d b y th e H T 9 5 8 0
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April 28, 2000
Preliminary
SPI input buffer register (read only)
Address 0038H 0039H 003AH 003BH Register Name SPI-IN3 SPI-IN2 SPI-IN1 SPI-IN0 Bit7 D7 D7 D7 D7 Bit6 D6 D6 D6 D6 Bit5 D5 D5 D5 D5 Bit4 D4 D4 D4 D4 Bit3 D3 D3 D3 D3 Bit2 D2 D2 D2 D2 Bit1 D1 D1 D1 D1 Bit0 D0 D0 D0 D0
HT9580
State on POR 0000 0000 0000 0000 0000 0000 0000 0000
The SPI-IN3~0 are used when receiving data on the serial bus. When SPI transmits only valid data writes to the register SPI-OUT3~0, "START" will initiate the SPI data transmission from HT9580 to FLEXTM decoder. After completion of the 4-byte data transfer, the "SPIFG" status bit will be set and the internal signal "REQST" will generate a falling edge signal for NMI. The bit7 of SPI-IN3 is MSB and bit0 of SPI-IN0 is LSB.
S P IF G
REQST (N M I) REQST ( r e g is te r ) START ( r e g is te r )
SCK M IS O d e c o d e r) MOSI H T9580) S P I-IN 3 ~ 0 S P I-O U T 3 ~ 0 MSB MSB 2 2 1 1 LSB LSB
(fro m (fro m
S S (to d e c o d e r) (fro m SRDY d e c o d e r)
S P I p a c k e t e x c h a n g e in itia te d b y th e H T 9 5 8 0
31
April 28, 2000
Preliminary
The POCSAG paging code A transmission using the CCIR Radio paging Code No.1 (POCSAG code) is generated in acPR EAM BLE 1 0 1 0 .........1 0 1 0 1 0 1 0 1 0 Synch CW CW CW CW CW CW BATCH1 BATCH2
HT9580
cordance with the following rules (see the following Figure).
LAST BATCH
FRAM E0 B it N u m b e r A d d re s s c o d e w o rd M e s s a g e c o d e w o rd Id le c o d e w o r d S y n c h c o d e w o rd 0 0 1 1 0 2 to 1 9 1 8 A d d r e s s B its 20
FRAM E1 2 0 /2 1 2 F u n c tio n B its 10 10 2 2 to 3 1 CRC CRC
FRAM E7 32 b its P P b its
M e s s a g e B its 3 1 Id le c o d e 31 S ynch code
B it p a tte r n B it p a tte r n
POCSAG code structure The transmission is started by sending a preamble, consisting of at least 576 continuously alternating bits (10101010...). The preamble is followed by an arbitrary number of batch blocks. Only complete batches are transmitted. Each batch comprises 17 code-words of 32 bits each. The first code-word is a synchronization code-word with fixed pattern. The sync word is followed by 8 frames (0~7) of 2 code-words each, containing message information. A code-word in a frame can either be an address, message or idle code-word. Idle code-words also have fixed patterns and are used to fill empty frames or separate messages. Bit 20 (MSB) 0 0 1 1 Bit 21 (LSB) 0 1 0 1 Address code-words are identified by an MSB of logic 0 and are coded as shown in the POCSAG code structure figure. A user address or RIC (Receiver Identity Code) consists of 21 bits. Only the upper 18 bits are encoded in the address code-word (bits 2 to 19). The lower 3 bits designate the frame number in which the address is transmitted. Four different call types can be distinguished on each user address. The call type is determined by two functional bits in the address code-word (bits 20 and 21). The POCSAG standard recommends the use (in Taiwan) of combinations of data formats and function bits, as shown in the following table. Other combinations will be set by SPF16~SPF19. Call Type Numeric Alert only Alert only Alpha-numeric Data Format 4-bit package 3/4 3/4 7-bit package
Data formats and function bits
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April 28, 2000
Preliminary
Alert-only calls consist of a single address code-word. Numeric and alphanumeric calls have message code-words following the address. Message code-words are identified by an MSB of logic 1. The message information is stored in a 20-bit field (bits 2 to 21). The data format is determined by the call type: 4 bits per digit for numeric message and 7 bits per (ASCII) charact e r f o r a l p ha num er i c m es s a g es . E a c h code-word is protected against transmission errors by 10 CRC check bits (bit 22 to 31) and an even parity bit (bit 32). This permits correction of a maximum of 2 random errors or up to 4 errors in a burst of 4 bits (a 4-bit burst error) per code-word.
* Error correction * On status
HT9580
In the ON status, the decoder pulses the receiver, quick charge and PLL enable outputs (respectively BS1, BS2 and BS3) according to the code structure and the synchronization algorithm. Data received serially at the data input (DI) is processed for call receipt.
* STB status
In the STB status the decoder will neither activate the receiver, quick charge or PLL enable outputs, nor process any data at the data input. The crystal oscillator remains active to permit communication with the microcontroller.
* Battery saving
Item Address code-word Message code-word
Description two random errors, or 4-bit burst errors (optional) two random errors, or 4-bit burst errors (optional) Error correction
In the HT9580, error correction methods have been implemented as shown in the table above. Random error correction is the default for both address and message code-word. In another method, burst error correction can be switched by SPF programming. Up to 4 erroneous bits in a 4-bit burst can be corrected. The error type detected for each code-word is identified in the message data output to the microcontroller, allowing rejection of calls with too many errors.
* Operating states
Current consumption is reduced by switching the STB internal decoder sections whenever the receiver is not enabled. To further increase battery efficiency, reception and decoding of an address code-word is stopped as soon as the uncorrected address field differs by more than 3-bits from the enabled RICs. If the next code-word has to be received again, the receiver is re-enabled, thus observing the programmed establishment times tBS1 , tBS2 and tBS3.
* Data reception and buffer
Reception of a valid paging call is signaled to the microcontroller by means of an interrupt signal. The received address and message code-word can then be read via a 46 bytes message buffer (from 0040H to 006DH) for decoder data message. If the mC did not read the previous message within one code-word time from the message buffer, the message buffer data will be overwritten.
* Bit rates
ON status STANDBY status The operating state is determined by control address (0019H) bit 0 and monitored by bit 3 of address (0019H).
The HT9580 can be configured for data rates of 512, 1200 or 2400 bit/s by SPF programming. These data rates are derived from 32.768kHz, 76.8kHz or 153.6kHz oscillator frequencies.
* Input data processing
Truth table for decoder operating status ON Input 0 1 Operating Status On state STANDBY state
33
The input data is noise filtered by means of a digital filter. Data is sampled at 16 times the data rate and averaged by majority decision.
April 28, 2000
Preliminary
The filtered data is used to synchronize an internal clock generator by monitoring transitions. The recovered clock phase can be adjusted in steps of 1/8, 3/32, 1/16, or 1/32 bit period per received bit. All step size are used when bit synchronization has not been achieved, the smallest when a valid data sequence has been detected.
* Erroneous code-words * Message receiving mode
HT9580
The receiving message mode (numeric or alpha-numeric) depends on bits SPF16~SPF19. If one of these bits from SPF16~SPF19 is cleared to low, the decoder will be in numeric package receiving mode. Otherwise, the decoder is in the alphanumeric receiving mode. An example is shown below:
Function Bits Bit 20 (MSB) SPF16=0 SPF17=0 SPF18=1 SPF19=1 0 0 1 1 Bit 21 (LSB) 0 1 0 1 Message Receiving Format Numeric (4-bit) Numeric (4-bit) Alphanumeric (7-bit) Alphanumeric (7-bit)
Upon receipt of erroneous uncorrectable code-words, call termination occurs according to the conditions given below: SPF08 SPF09 Description Any two consecutive code-words or the code-word directly following the address code-word in error Any single code-word in error Any two consecutive code-words in error
0
X
1 1
0 1
The decoder data output format is determined by the value SPF16~SPF19. When it is logic low, the 4-bit (numeric) package will be selected. Otherwise, the 7-bit (alphanumeric) package is selected. The following tables illustrate the above two different conditions.
Message code-word on the message buffer (numeric receiving mode) Bit7 Error Flag Bit6 0 Bit5 0 Bit4 0 Bit3 D3 Bit2 D2 Bit1 D1 Bit0 D0
Message code-word on the message buffer (alphanumeric receiving mode) Bit7 Error Flag Bit6 D6 Bit5 D5 Bit4 D4 Bit3 D3 Bit2 D2 Bit1 D1 Bit0 D0
* Synch word indication
The synch word recognized by the HT9580 is Bit No. Bit Bit No. Bit 0 0 16 0 1 1 17 0 2 1 18 0 3 1 19 1 4 1 20 0 5 1 21 1 6 0 22 0 7 0 23 1
the standard POCSAG synchronization code-word as shown in the following table. 8 1 24 1 9 1 25 1 10 0 26 0 11 1 27 1 12 0 28 1 13 0 29 0 14 1 30 0 15 0 31 0
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April 28, 2000
Preliminary
* Idle word indication
HT9580
The idle word recognized by the HT9580 is a Bit No. Bit Bit No. Bit 0 0 16 1 1 1 17 1 2 1 18 0 3 1 19 0 4 1 20 0 5 0 21 0 6 1 22 0 7 0 23 1
standard POCSAG idle code-word as shown in the following table. 8 1 24 1 9 0 25 0 10 0 26 0 11 0 27 1 12 1 28 0 13 0 29 1 14 0 30 1 15 1 31 1
* Error indication
After error correction, any code-word containing more than 2-bit random errors or 4-bit burst errors (option) in the address or message code-word may be indicated from the error flag position.
* Decoder and mC interface
The HT9580 has two mC interface available.
B it 5 DR_FG (0 0 0 6 H ) B it 4 BF_FG (0 0 0 6 H ) B it 7 B it 6 BL B it 5 OR B it 4
One is the pager control address (0019H), which controls the operation and configuration of the decoder. The other is the pager message buffer address (from 0040H to 006DH), which receives the message data of calls in the parallel mode. The data ready (DR_FG) and battery fail (BF_FG) interrupt flags are in the interrupt flag register (0006H).
0019 H B it 3 STB B it 2 B it 1 RES B it 0 ON
B it 0 B it 1 B it 2 B it 3 B it 4 B it 5 B it 6 B it 7 M e s s a g e B u ffe r (4 6 B y te s ) m C (N M I) 1 mC PA7 (W a k e u p ) P a g e r S y s te m CLK D ebounce C ir c u it D a ta R e a d y In te rru p t SPIR EQ ST V V
IL IH
POCSAG D e c o d e r D a ta O u tp u t
D ecoder
DI BA BS BS BS
L 1 2
3 RSSI
RF CKT.
= 0 .9 V = 1 .0 V
B A F ( B a tte r y F a il In te r r u p t)
Note: The value of 0019H-bit3 STB is set when decoder enters the standby mode and cleared when decoder enters the ON mode. The value of 0006H-bit4 BF_FG is dependent on the BAF pin ststus. The value of 0019H-bit5 OR is always changed by an out of range signal. The value of 0019H-bit6 BL is cleared 0" by the decoder Battery low signal and set 1" when the mC sets this bit high. The value of 0006H-bit5 DR_FG is set 1" by the decoder Data-Ready interrupt signal and cleared 0 when the mC clears DR_FG.
35 April 28, 2000
Preliminary
The decoder control address (0019H) contains a battery low flag (BL), an out of range flag (OR), decoder standby flag (STB), a decoder software reset (RES), and a decoder on/off control bit (ON). The data ready and battery fail flag are in the interrupt flag register (0006H). It not only records the status information but controls the operation of the decoder. If the flag status of the battery fail (BF_FG) changes from 0 to 1, the following conditions occur. The pager controller generates an interrupt if the value of the data ready interrupt is 0. The pager controller does not generate any interrupt and no data is transmitted to it if the value of the data ready interrupt is 1.
HT9580
On the other hand, if the status of the battery fail flag (BF_FG) changes from 1 to 0, the internal node PA.7 of the pager controller will supply a wake-up function. After the decoder asserts the data ready request, the data ready interrupt is generated and the DR_FG bit (bit 5 of 0006H) is set high; then the data ready interrupt subroutine runs to process the call data on the message buffer and resets the DR_FG bit low. The functional bits (ON, RES) and indication bits ( STB, OR, BL, BF_FG and DR_FG) are all used to control the status of the decoder which is operated through the pager control address as described in the following table.
INT flag register (0006H) Symbol BF_FG Bit 4 R/W R Description Battery fail indication bit Once the decoder detects that the battery fail condition occurred, the BF_FG will go high. Data ready interrupt indication bit When a valid call is detected, data transfers to the message buffer. The DR_FG bit goes high when the message is terminated within 46 bytes, one batch is at the end during the message receiving or the data buffer is full if the data length is more than 46 bytes. The mC software should read the data on the message buffer within one POCSAG message codeword (32-bit) time. The mC software has to clear the DR_FG bit low.
DR_FG
5
R/W
Decoder control register (0019H) Symbol Bit R/W Description On/Off control bit This bit selects the ON or STANDBY state of the decoder 0: ON state 1: STANDBY RES If SPI circuit is enabled, it would be better if this bit is set high to reduce power consumption. Resets the decoder core output The mC has to set the RES bit low and then high after the pager controller is turned on. The reset status must be released before writing data to the decoder configuration RAM.
ON
0
R/W
RES
1
R/W
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April 28, 2000
Preliminary
Symbol STB Bit 3 R/W R Description
HT9580
Standby indication bit When the value of the ON bit is 1, the system goes into the STANDBY state. The STANDBY state allows the mC to execute the configuration RAM setting. Out-of-range indication bit Whenever the decoder detects an out-of-range hold time, that is selected by the configuration registers SPF06 and SPF07. The out-of-range indication may be tested for an out-of-range condition whenever the interface enable of the decoder is active; otherwise OR is normally low. The out-of-range indication is set high by detection of valid data transmission. If the out-of-range indication bit changes the status from high to low or low to high, an interrupt will be generated and the out-of-range hold-off time-out counter starts to count. The bit is not valid when the SPI circuit is enabled. Battery low indication bit The battery low indication is periodically tested for a battery low condition. If the decoder encounters a battery low condition, the battery low indication bit is cleared low. The mC can only set the BL bit high. Attempting to clear this bit has no effect. The bit is not valid when the SPI circuit is enabled. Register allocation A00 0 A07 1 A14 0 A01 0 A08 0 A15 1 A02 0 A09 1 A16 0 A03 0 A10 0 A17 0 A04 0 A11 0 A05 0 A12 1 A06 0 A13 0
OR
5
R
BL
6
R/W
* User address format
A user address in the POCSAG code consists of 21 bits. Three of the 21 bits are coded in the frame number and are therefore not explicitly transmitted. In the decoder, the addresses A, B, C, D, E and F can use six different frames respectively. Every address has to be explicitly enabled by resetting the associated enable bit. Example: Address decimal value: RICA=10535 Binary equivalent (14-bit): 10100100100111 Binary equivalent (18+3-bit): 000000010100100100111
FA2 FA1 FA0 1 1 1
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April 28, 2000
Preliminary
* Test mode
HT9580
The test mode of the decoder is selected by setting the TS pin low at any time. In the test mode, the RF control outputs BS1 and BS3 are constantly set high, but BS2 is set low. After the TS pin is set high the decoder exits the test mode.
* Message data transfer
the received data (including address codeword and message codeword) length is terminated within 46 bytes, one batch is over or if the 46 bytes data buffer is full if data length is more than 46 bytes. If the data in the message buffer is terminated, the MSG_END (0031H) bit will set high. The address word indicates call address, functional bit setting, and decoder flags. The message code-words are received and concatenated to a valid call address word. The message words are derived from un-corrected message code-words.
The decoder outputs a deformatted address word and message words upon receipt of a valid call. The message data to be transferred is organized into 8-bit words and transferred to the message buffer address (0040H to 006DH). The data ready interrupt flag will be set high when
* Address word format
Bit7 Sync. State
Bit6
Bit5 Call Address
Bit4
Bit3 Dup. Call
Bit2 Valid Address
Bit1
Bit0
Function Code
Note: Bit0: Bit21 of the address code-word Bit1: bit20 of the address code-word Bit2: If this bit is 1, the address word is valid, oterwise the address word is not valid. Bit3: 1 for a duplicate code-word Bit7: 1 if an address code-word is received in the data fail mode Bit6 0 0 0 0 1 1 1 1 Bit5 0 0 1 1 0 0 1 1 Bit4 0 1 0 1 0 1 0 1 Call Address RIC A RIC B RIC C RIC D RIC E RIC F 3/4 3/4
* Interrupt indication
The HT9580 provides an internal data ready interrupt and a battery fail interrupt. The internal data ready interrupt and battery fail interrupt share the NMI location. Which interrupt occurred can be determined by checking the battery fail interrupt bit (BF_FG; bit 4 of 0006H) and the data ready interrupt bit (DR_FG; bit 5 of 0006H). Both interrupt bits are active high.
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April 28, 2000
Preliminary
* Out-of-range indication
HT9580
Option SPF00 SPF01 0 0 1 1 0 1 0 1
The out-of-range condition occurs when the time interval defined by SPF06, SPF07 is unable to receive sync code words. If sync code words are detected, the timer counter defined by SPF06, SPF07 will reset. This signal will be seen as a loss of RF signal indication and the power on reset is in an out-of-range condition until the sync code word is detected.
* Duplicate call suppression
Receiver Establishment Time TBS1 512 bps 7.81ms 15.63ms 31.25ms 62.50ms 1200/2400 bps 53.33ms 6.67ms 13.33ms 26.67ms
The HT9580 provides a duplicate call suppression with time-out facility, to identify duplicate call reception. In the display pager mode, duplicate call indication is achieved only via the mC interface. A call is assumed to be a duplicate if its latest address and function bit setting is equal to the previous received call within the time interval defined by SPF06, SPF07.
* Receiver, Quick charge and PLL signal control
Quick Charge Adjustment Time TBS2 512 bps 7.81ms 15.63ms 15.63ms 19.53ms 1200/2400 bps 1.67ms 6.67ms 11.67ms 13.33ms
Option SPF02 SPF03 0 0 1 1 0 1 0 1
Pager receiver, quick charge circuit, and RF PLL circuit can be controlled independently via enable outputs BS1, BS2, and BS3 respectively. Their operating period are optimized according to the synchronization mode of the decoder. Each enable signal has its own programmable establishment time.
PLL Establishment Time TBS3 512 bps 0ms 31.25ms 46.87ms 62.50ms 1200/2400 bps 0ms 26.67ms 40.00ms 53.33ms
Option SPF04 SPF05 0 0 1 1 0 1 0 1
R.F. timing chart
D a ta In T BS1 T BS2 T BS3
BS3 BS2
D a ta B its
BS1
39
April 28, 2000
Preliminary
Decoder configuration RAM The decoder contains a 21-byte RAM to store six user addresses, six frame numbers, and specially programmed function bits (SPF00~SPF19) for the decoder application configuration. The data Address 001AH 001BH 001CH 001DH 001EH 001FH 0020H 0021H 0022H 0023H 0024H 0025H 0026H 0027H 0028H 0029H 002AH 002BH 002CH 002DH 002EH Bit7 ENA A07 A15 ENB B07 B15 ENC C07 C15 END D07 D15 ENE E07 E15 ENF F07 F15 SPF00 SPF08 SPF16 Bit6 A00 A08 A16 B00 B08 B16 C00 C08 C16 D00 D08 D16 E00 E08 E16 F00 F08 F16 SPF01 SPF09 SPF17 Bit5 A01 A09 A17 B01 B09 B17 C01 C09 C17 D01 D09 D17 E01 E09 E17 F01 F09 F17 SPF02 SPF10 SPF18 Bit4 A02 A10 FA2 B02 B10 FB2 C02 C10 FC2 D02 D10 FD2 E02 E10 FE2 F02 F10 FF2 SPF03 SPF11 SPF19 memory is mapped 001AH~002EH. to the
HT9580
address
The configuration memory mapping table is shown below. Bit Definition Bit3 A03 A11 FA1 B03 B11 FB1 C03 C11 FC1 D03 D11 FD1 E03 E11 FE1 F03 F11 FF1 SPF04 SPF12 X Bit2 A04 A12 FA0 B04 B12 FB0 C04 C12 FC0 D04 D12 FD0 E04 E12 FE0 F04 F12 FF0 SPF05 SPF13 X Bit1 A05 A13 X B05 B13 X C05 C13 X D05 D13 X E05 E13 X F05 F13 X SPF06 SPF14 X Bit0 A06 A14 X B06 B14 X C06 C14 X D06 D14 X E06 E14 X F06 F14 X SPF07 SPF15 X
40
April 28, 2000
Preliminary
Description of the special programmed function bits (SPFn) The following features can be selected by appropriate programming of the specially programmed function bits:
* SPF00~SPF01 * SPF10
HT9580
1: 4-bit burst error correction for address and message code-word 0: 2-bit random error correction for address and message code-word
* SPF11
Receiver (BS1) establishment time (for the BS2~BS3 options, refer to SPF02~SPF05) 00: 7.81ms/512 53.33ms/1200/2400 01: 15.63ms/512 6.67ms/1200/2400 10: 31.25ms/512 13.33ms/1200/2400 11: 62.50ms/512 26.67ms/1200/2400 Note: The recommendatory setting is 11.
* SPF02~SPF03
1: Out-of-range Hold-off period according to SPF06 and SPF07 0: Out-of-range Hold-off period is 0 regardless of SPF06 and SPF07 Baud rate selection bits(SPF12,SPF13,SPF14)
SPF12 0 0 0 0 1 1 1 SPF13 0 0 1 1 0 0 1 SPF14 0 1 0 1 0 1 0 Connected Crystal (Hz) 32768 76.8k 76.8k 76.8k 153.6k 153.6k 153.6k Baud Rate (bps) 512 512 1200 2400 512 1200 2400
RF dc level adjustment (BS2) enable time 00: 7.81ms/512 1.67ms/1200/2400 01: 11.71ms/512 6.67ms/1200/2400 10: 15.63ms/512 11.67ms/1200/2400 11: 19.53ms/512 13.33ms/1200/2400
* SPF04~SPF05
PLL (BS3) establishment time 00: 0ms/512 0ms/1200/2400 01: 31.25ms/512 26.67ms/1200/2400 10: 46.87ms/512 40.00ms/1200/2400 11: 62.50ms/512 53.33ms/1200/2400
* SPF06~SPF07
Note: The (SPF12, SPF13, SPF14) = (0, 1, 0) when power on reset * SPF15 Non-inverting or inverting data input selection 1: Inverting input selected for DI from RF circuit, referring to DI 0: Non-inverting input selected for DI from RF circuit reserved, should be 0
* SPF16~SPF19
The duplicate call suppress time-out and out-of-range hold-off time-out 00: 30s/512/1200 15s/2400 01: 60s/512/1200 30s/2400 10: 120s/512/1200 60s/2400 11: 240s/512/1200 120s/2400
* SPF08~SPF09
Message receiving mode selection depending on the function code (bit20, bit21)
0 1 SPF16 Function Code (0, 0) is Function Code (0, 0) is an a numeric message alpha-numeric message SPF17 Function Code (0, 1) is Function Code (0, 1) is an a numeric message alpha-numeric message SPF18 Function Code (1, 0) is Function Code (1, 0) is an a numeric message alpha-numeric message SPF19 Function Code (1, 1) is Function Code (1, 1) is a numeric message analpha-numeric message
0x: Any two consecutive code-words or the code-word directly following the address code-word in error 10: Any single code-word in error 11: Any two consecutive code-words in error
41
April 28, 2000
Preliminary
CPU Core
The HT9580 is a high performance pager controller specifically designed for use in new generation radio pagers. It is based on the M6502 core. The 6502 Microprocessor offers complete hardware and software capability with existing 6500 series of products as well as significant enhancements. Instruction register and decoder Instructions fetched from memory are gated onto the internal bus. These instructions are latched into the instruction register then decoded, along with timing and interrupt signals, to generate control signals for the various registers. Timing control unit The timing control unit keeps track of the instruction cycle being monitored. The unit is set to 0 each time an instruction fetch is executed and is advanced at the beginning of each input clock pulse for as many cycles as required to complete the instruction. Each data transfer between registers depends upon decoding the contents of both the Instruction Register and the Timing Control Unit. There are three major clocks in the mC as follows:
* Phase 2 In (PHI2 (IN))
HT9580
bus memory. In the low state the data bus has valid data from the mC to be stored at the addressed memory location. Parameter tcyc tad tah tdis tdih tdod tdoh tdenbd twed tsyd tsyh tvd tvh tsos tsoh trds trdh tress tresh Description Clock cycle time (min) Address delay time Address hold time Read data in setup time Read data in hold time Write data out delay time Write data out hold time DATAEN delay time WE_N delay time SYNC delay time SYNC hold time VPB delay time VPB hold time SOB_N setup time SOB_N hold time RDY setup time RDY hold time RES_N setup time RES_N hold time Timing parameter annotations Arithmetic and logic unit All arithmetic and logic operations take place within the ALU including incrementing and decrementing internal registers (except for the program counter). The ALU has no internal memory and is used only to perform logical and transient numerical operations.
This signal is from the OSC1 input pin of HT9580. The PHI1 (OUT) and PHI2 (OUT) are derived from this signal.
* Phase 2 Out (PHI2 (OUT))
This signal is generated from PHI2 (IN). PHI2 (IN) provides the system timing. There is a slight delay from PHI2 (IN).
* Phase 1 Out (PHI1 (OUT))
Inverted PHI2 (OUT) signal. There is a slight delay from PHIN2 (IN). Read/write This signal is normally in a high state indicating that the mC is reading data from the data
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April 28, 2000
Preliminary
tc
yc
HT9580
CLK ta
d
ta
h
ADDR
RD
A d d re s s td
is
W R A d d re s s
DATAI
READ td
ih
td
od
DATAO td DATAEN tw ts ts SYNC, VPB RDY, RES_N SO B_N trd h , tre trd s , tre
ss sh yh yd enbd
W R IT E td
oh
W E_N , tv
h
ed
, tv
d
, ts
oh
, ts
os
M6502 read and write cycle Accumulator The Accumulator is a general purpose 8-bit register which stores the results of most arithmetic and logic operations. In addition, the accumulator usually contains one of the two data words used in these operations. Index register There are two 8-bit Index Register (X and Y) which may be used to count program steps or to provide an index value to be used in generating an effective address. When executing an instruction which specifies indexed addressing, the mC fetches the opcode and the base address, and modifies the address by adding the index register to it prior to performing the desired operation. Pre- or post-indexing of indirect addresses is possible.
43
Processor status register The 8-bit processor status register contains seven status flags. Some of the flags are controlled by the program, others may be controlled both by the program and the mC. The HT9580 instruction set contains a number of conditional branch instructions which are designed to allow testing of these flags. Program counter The 16-bit program counter register provides the addresses which step the mC through sequential program instructions. Each time the HT9580 fetches an instruction from the program memory, the lower byte of the program counter (PCL) is placed on the low-order bits of the address bus and the higher byte of the program counter (PCH) is placed on the high-order
April 28, 2000
Preliminary
8 bits. The counter is incremented each time an instruction or data is fetched from the program memory. Stack pointer The stack pointer is an 8-bit register which is used to control the addressing of the variable-length stack. The stack pointer is automatically incremented and decremented under control of the microprocessor to perform stack manipulations under direction of either the program or interrupt (NMI and IRQ). The stack allows simple implementation of nested subroutines and multiple level interrupts. The stack pointer is initialized by the users software.
7 A 7 Y 7 X 15 PCH 15 7 0 0 0 0 0 0 1 S 0 8 7 PCL 0 S ta c k P o in te r 0 P ro g ra m C o u n te r P C 0 In d e x R e g is te r X 0 In d e x R e g is te r Y
HT9580
Status register N V Z: Zero I: IRQ E B 1=true 1=true 1=disable 1=true 1=BRK, 0=IRQ D I Z C Note: C: Carry
D: Decimal mode B: BRK command V: Overflow N: Negative
E: Expansion bit (reserved) 1=true 1=negative
0 A c c u m u la to r A
T h e w id th o f th e c o r r e s p o n d in g r e g is te r s
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April 28, 2000
Preliminary
Interrupt System
The HT9580 is capable of directly addressing 64 Kbytes of memory. The address space has special significance within certain addressing modes, as follows: Reset and interrupt vectors The reset and interrupt vectors use the majority of the fixed addresses between FFFA and FFFF. Stack The stack may use memory from 01D0 to 01FF. The effective address of stack and stack relative addressing modes will always be within this range. Interrupt request - IRQ This CMOS compatible signal requests that an interrupt sequence begin within the mC. The IRQ is sampled during PHI2 operation; if the interrupt flag in the processor status register is 0, the current instruction is completed and the interrupt sequence begins during PHI1. The program counter and processor status register are stored in the stack. The mC will then set the interrupt mask flag high so that no further interrupts may occur. At the end of this cycle, the PCL will be loaded from address FFFE, and PCH from location FFFF, transferring program control to the memory vector located at these addresses. The IRQ signal going low causes 3 bytes of information to be pushed onto the stack before jumping to the interrupt handler. The first byte is the high byte in the program counter. The second byte is the program counter low byte. The third byte is the status register value. These values are used to return the processor to its original state prior to the IRQ interrupt. Non-maskable interrupt - NMI A negative-going edge on this input requests that a non-maskable interrupt sequence be generated within the mC. The NMI is sampled during PHI2; the current instruction is completed and the interrupt sequence begins during PHI1. The Program Counter is loaded with
45
HT9580
the interrupt vector from locations FFFA (low byte) and FFFB (high byte), thereby transferring program control to the non-maskable interrupt routine. The NMI is generated from data ready interrupt or battery fail interrupt flag (0006H). However, it should be noted that this is an edge-sensitive input. As a result, another interrupt will occur if there is another negative-going transition and the program has not returned. Also, no interrupt will occur if NMI is low and a negative-going edge has not occurred since the last non-maskable interrupt. The NMI signal going low causes 3 bytes of information to be pushed onto the stack before jumping to the interrupt handler. The first byte is the high byte in the program counter. The second byte is the program counter low byte. The third byte is the status register value. These values are used to return to its original state prior to NMI interrupt. Data address space The mC internal address bus consists of A0~A15 forming a 16-bit address bus for memory and I/O exchanges on the data bus. The output of each address line is CMOS compatible. The Address output pins of HT9580 (A0~A15) derive from mC internal address pins A0~A15. The extended address pins (RA14~RA18) are the combination of bank point registers (0015H, 0016H) and internal address. The extended address pins are used to access internal/external SRAM or Mask ROM (Character ROM). The data lines constitute 8-bit bidirectional data bus for use during exchanges between the mC and peripherals. The outputs are three-state buffers capable of driving CMOS load. The Program Address and Data Address space is continuous throughout the 64 Kbyte address space. Words, arrays, records, or any data structures may span the 64 Kbytes address space. The following addressing mode descriptions provide additional detail as to how effective addresses are calculated. Fifteen addressing modes are available for the HT9580 as illustrated on the next page.
April 28, 2000
Preliminary
Addressing modes The M6502 supports fifteen (15) addressing modes, shown in table below. In interpreting this table you should note that:
* The byte following a 2 byte opcode = IAL (typ.) * The 2 bytes following a 3 byte opcode = BAL
HT9580
* A number in parenthesis indicates that the
contents of the location pointed to by the number are to be used. For example (12H) indicates the contents of address 12H.
* A comma in the address is used to indicate the
and BAH (typ.)
* Standard assembly notation is used
high and low byte of an address. For example (01H, AAH) indicates the contents of address 01AAH.
Mode IMP ACC IMM ZPG ZPX
Description IMPLIED: The data is implied in the opcode (example: CLC) ACCUMULATOR: The accumulator is used as the source data. (data=AREG) IMMEDIATE: The byte following the opcode is the data. (data=IAL) ZERO PAGE: The first 256 RAM locations (0000H~00FFH) are used for fast access and small code size. The upper 8-bit of the address are always zero. [data=(00, IAL)] ZERO PAGE INDIRECT X: The X register is added to the byte following the opcode to give a new zero page address. Note that the upper 8-bit of the address are always zero. [data=(00, IAL+X)] ZERO PAGE INDIRECT Y: The Y register is added to the byte following the opcode to give a new zero page address. Note that the upper 8-bit of the address are always zero. Only the LDX and the STX opcodes use this mode. [data=(00, IAL+Y)] ABSOLUTE: The two bytes following the opcode give the absolute address of the data. [data=(BAH, BAL)] ABSOLUTE X: The X register is added to the two bytes following the opcode to produce a new 16-bit address. {data=[(BAH, BAL)]+X} ABSOLUTE Y: The Y register is added to the two bytes following the opcode to produce a new 16-bit address. {data=[(BAH, BAL)]+Y} ABSOLUTE INDIRECT: The two bytes following the opcode are used as a pointer to memory. Only the JMP opcode uses this mode. [data=(BAH, BAL)] INDEXED ABSOLUTE INDIRECT X: The two bytes following the opcode are added to the X register to yield a new 16-bit address. The contents of this address and the following one are used as an indirect address. Only the JMP opcode uses this mode. {data=[(BAH, BAL+X+1), (BAH, BAL+X)]} INDIRECT: The byte following the opcode is used as a pointer to the zero page. The contents of this address and the following one are used as the address to finally access the data. {data=[(IAL+1), (IAL)]}
ZPY ABS ABX ABY ABI
AIX
IND
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April 28, 2000
Preliminary
Mode Description
HT9580
INX
INDIRECT X: The byte following the opcode is added to the X register to produce a new zero page address. The contents of this address and the following one are used as the address to finally access the data. Note that when the X register is added to the byte following the opcode, the upper byte of the address is always zero. {data=[(00, IAL+X+1), (00, IAL+X)]} INDIRECT Y: The byte following the opcode is a zero page address. The contents of this location and the next one produce a 16-bit address which is then added to the Y register to finally obtain the data. {data=<[(00, IAL+1), (00, IAL)]+Y>} RELATIVE: The byte following the opcode is added in 2's complement fashion to the PC. The byte is sign extended. Used by branching instructions.
INY REL
47
April 28, 2000
Preliminary
Application Circuits
OSC1, OSC2 require an external resistor
V
DD
HT9580
(1 .5 V ) 470mH S c h o ttk y D io d e LX OUT D C /D C VSS + 3V
+ + -
22mF
22mF 1,25,56
R H 5R 302 S la v e LCD D is p la y H o lte k Pager M a s te r
1 .5 V 65 64 63 62 58 61
LCD
D r iv e r
LCD D0~ LCD RES LCD LCD LCD LCD
D7 _R ET _C _C _C _A 0
_E
VDD W S 0 (M a s te r) S 1 ( S la v e ) L
BS1 BS2 BS3 DI BAL RSSI
VDD RF R e c e iv e r VSS 1 .5 V
BAF BZ
59 55 60 79 80 77 V 76 26 N o rm a l T y p e R o m le s s
DD
V
DD
510W
0 .1 m F
H T93LC 46
CS EEPROM SK DI DO VSS
49 46 47 48
PB4 PB1 PB2 PB3 PB0 PB5~PB7
D A_O U T X2 X1 OSC1 OSC2
0 .1 m F 7 6 .8 k H z
B uzzer
44 66 SW 1 SW 2 SW 3 V
DD
PA3~PA5 TM R1 TS PA0 PA1 PA2 D0~D7 A0~A15 PSEN P_M O DE
72 71 70
HT9580
D0~D7 20 A0~A15 CE OE H T27LC 512 P ro g ra m ROM
100kW 0 .1 m F
73
RESET
53 1 .5 V 1 .5 V 1kW 680W 54
PC0 PC1
A0~A13 R A14~R A17 D0~D7 M ASK_CE SR AM _C E 18 17 16 19
A0~A17 D0~D7 ROMCE RAMCE WE OE N o te : T h e e x te r n a l m e m o r y is o p tio n a l
M askR A M
Lam p
M o to r M
R /W VSS 27,57,78 OE
48
April 28, 2000
Preliminary
HT9580
OSC1, OSC2 do not require a resistor. The OSC1 clock comes from an internal pad DF only
V
DD
(1 .5 V ) 470mH S c h o ttk y D io d e LX OUT D C /D C VSS + 3V
+ + -
22mF
22mF 1,25,56
R H 5R 302 S la v e LCD D is p la y H o lte k Pager M a s te r VDD W
1 .5 V 65 64 63 62 58 61
LCD
D r iv e r
LCD D0~ LCD RES LCD LCD LCD LCD
D7 _R ET _C _C _C _A 0
_E
S 0 (M a s te r) S 1 ( S la v e ) L
BS1 BS2 BS3 DI BAL RSSI
VDD RF R e c e iv e r VSS 1 .5 V
BAF BZ
59 55 60 79 80 0 .1 m F 7 6 .8 k H z B uzzer 510W 0 .1 m F
V
DD
H T93LC 46
CS EEPROM SK DI DO VSS
49 46 47 48
PB4 PB1 PB2 PB3 PB0 PB5~PB7
D A_O U T X2 X1 DF OSC1 OSC2 P_M O DE
1 5 3 .6 k H z V 26
DD
44 66 SW 1 SW 2 SW 3 V
DD
PA3~PA5 TM R1 TS PA0 PA1 PA2
N o rm a l T y p e R o m le s s
72 71 70
HT9580
D0~D7 A0~A15 PSEN 20
D0~D7 A0~A15 CE OE H T27LC 512 P ro g ra m ROM
100kW 0 .1 m F
73
RESET
53 1 .5 V 1 .5 V 1kW 680W 54
PC0 PC1
A0~A13 R A14~R A17 D0~D7 M ASK_CE SR AM _C E 18 17 16 19
A0~A17 D0~D7 ROMCE RAMCE WE OE N o te : T h e e x te r n a l m e m o r y is o p tio n a l
M askR A M
Lam p
M o to r
M VSS 27,57,78
R /W OE
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April 28, 2000
Preliminary
The SPI application circuits
V
DD
HT9580
(1 .5 V ) 470mH S c h o ttk y D io d e LX OUT D C /D C VSS + 3V
+ + -
22mF
22mF 1,25,56
1 .5 V
R H 5R 302 S la v e LCD D is p la y H o lte k Pager M a s te r
LCD
D r iv e r
LCD D0~ LCD RES LCD LCD LCD LCD
D7 _R ET _C _C _C _A 0
_E
VDD W S 0 (M a s te r) S 1 ( S la v e ) L SC MO M IS SRD RS
SS
65 64 63 62 58 61 1 .5 V F le x TM Decoder
VDD RF R e c e iv e r VSS
K SI O Y SI
BAF BZ
59 55 60 79 80 77 V 76 26 N o rm a l T y p e R o m le s s
DD
V
DD
510W
0 .1 m F
H T93LC 46
CS EEPROM SK DI DO VSS
49 46 47 48
PB4 PB1 PB2 PB3 PB0 PB5~PB7
D A_O U T X2 X1 OSC1 OSC2
0 .1 m F 7 6 .8 k H z
B uzzer
44 66 SW 1 SW 2 SW 3 V
DD
PA3~PA5 TM R1 TS PA0 PA1 PA2 D0~D7 A0~A15 RESET PSEN P_M O DE
72 71 70
HT9580
D0~D7 20 A0~A15 CE OE H T27LC 512 P ro g ra m ROM
100kW 0 .1 m F
73
53 1 .5 V 1 .5 V 1kW 680W 54
PC0 PC1
A0~A13 R A14~R A17 D0~D7 M ASK_CE SR AM _C E 18 17 16 19
A0~A17 D0~D7 ROMCE RAMCE WE OE N o te : T h e e x te r n a l m e m o r y is o p tio n a l
M askR A M
Lam p
M o to r M
R /W VSS 27,57,78 OE
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April 28, 2000
Preliminary
Detailed Instruction Operation
The table below provides a brief description of each opcode. The first column lists the name or the assembler mnemonic for the instruction. The second column lists the opcode in hexadecimal. The third column lists the address mode for the instruction. The flags column indicates which of the 8-bit of flags are updated by the instruction. Legend: + 6 7 (R) No change (R) Updated (R) From memory bit 6 (R) From memory bit 7
HT9580
The number of bytes column gives the number of bytes for the opcode. The number of cycles column gives the number of clock cycles for the opcode. (A+b indicates one additional cycle when a branch is taken within the same page, or 2 cycles if the branch is to a different page.) The last column are the description or brief descriptions of the opcode. The operator notation is as follows: => + | & ^ ! << >> < > A C X Y S M assignment 2s complement add 2s complement subtract Bitwise OR Bitwise AND Bitwise exclusive OR Bitwise invert (ones complement) Left rotate Right rotate Left shift Right shift Accumulator Carry flag X index register Y index register Stack pointer Memory
51
April 28, 2000
Preliminary
Name ADC ADC ADC ADC ADC ADC ADC ADC ADC AND AND AND AND AND AND AND AND AND ASL ASL ASL ASL ASL BBR0 BBR1 BBR2 BBR3 BBR4 BBR5 BBR6 BBR7 BBS0 BBS1 BBS2 BBS3 BBS4 Opcode 69 65 75 6D 7D 79 72 61 71 29 25 35 2D 3D 39 32 21 31 0A 06 16 0E 1E 0F 1F 2F 3F 4F 5F 6F 7F 8F 9F AF BF CF Addr Mode IMM ZPG ZPX ABS ABX ABY IND IDX IDY IMM ZPG ZPX ABS ABX ABY IND IDX IDY ACC ZPG ZPX ABS ABX REL REL REL REL REL REL REL REL REL REL REL REL REL Flags NVEBDI ZC ++ ++ ++ ++ ++ ++ ++ ++ ++ + + + + + + + + + + + + + + ++ ++ ++ ++ ++ ++ ++ ++ ++ + + + + + + + + + No. Bytes 2 2 2 3 3 3 2 2 2 2 2 2 3 3 3 2 2 2 1 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 No. Cyc. 2 3 4 4 4 4 5 6 5 2 3 4 4 4 4 5 6 5 2 5 6 6 7 5+b 5+b 5+b 5+b 5+b 5+b 5+b 5+b 5+b 5+b 5+b 5+b 5+b Description
HT9580
A+M+C=>A, C Add with carry A+M+C=>A, C Add with carry A+M+C=>A, C Add with carry A+M+C=>A, C Add with carry A+M+C=>A, C Add with carry A+M+C=>A, C Add with carry A+M+C=>A, C Add with carry A+M+C=>A, C Add with carry A+M+C=>A, C Add with carry A&M=>A A&M=>A A&M=>A A&M=>A A&M=>A A&M=>A A&M=>A A&M=>A A&M=>A AND A with M AND A with M AND A with M AND A with M AND A with M AND A with M AND A with M AND A with M AND A with M
++ ++ ++ ++ ++ -
A<1=>A shift left 1, C<-7, 0<-zero M<1=>M shift left 1, C<-7, 0<-zero M<1=>M shift left 1, C<-7, 0<-zero M<1=>M shift left 1, C<-7, 0<-zero M<1=>M shift left 1, C<-7, 0<-zero If M (0)=0, PC<=PC+Off (Off sign ext) If M (1)=0, PC<=PC+Off (Off sign ext) If M (2)=0, PC<=PC+Off (Off sign ext) If M (3)=0, PC<=PC+Off (Off sign ext) If M (4)=0, PC<=PC+Off (Off sign ext) If M (5)=0, PC<=PC+Off (Off sign ext) If M (6)=0, PC<=PC+Off (Off sign ext) If M (7)=0, PC<=PC+Off (Off sign ext) If M (0)=1, PC<=PC+Off (Off sign ext) If M (1)=1, PC<=PC+Off (Off sign ext) If M (2)=1, PC<=PC+Off (Off sign ext) If M (3)=1, PC<=PC+Off (Off sign ext) If M (4)=1, PC<=PC+Off (Off sign ext)
52
April 28, 2000
Preliminary
Name BBS5 BBS6 BBS7 BCC BCS BEQ BIT BIT BIT BIT BIT BMI BNE BPL BRA BRK BVC BVS CLC CLD CLI CLV CMP CMP CMP CMP CMP CMP CMP CMP CMP CPX CPX CPX CPY CPY Opcode DF EF FF 90 B0 F0 89 24 34 2C 3C 30 D0 10 80 00 50 70 18 D8 58 B8 C9 C5 D5 CD DD D9 D2 C1 D1 E0 E4 EC C0 C4 Addr Mode REL REL REL REL REL REL IMM ZPG ZPX ABS ABX REL REL REL REL IMP REL REL IMP IMP IMP IMP IMM ZPG ZPX ABS ABX ABY IND INX INY IMM ZPG ABS Imm ZPG Flags NVEBDI ZC 0 1 0 + + + + + 0 No. Bytes 3 3 3 2 2 2 2 2 2 3 3 2 2 2 2 1 2 2 1 1 1 1 2 2 2 3 3 3 2 2 2 2 2 3 2 2 No. Cyc. 5+b 5+b 5+b 2+b 2+b 2+b 2 3 4 4 4 2+b 2+b 2+b 2+b 7 2+b 2+b 2 2 2 2 2 3 4 4 4 4 5 6 5 2 3 4 2 3 Description
HT9580
If M (5)=1, PC<=PC+Off (Off sign ext) If M (6)=1, PC<=PC+Off (Off sign ext) If M (7)=1, PC<=PC+Off (Off sign ext) If C=0, PC<=PC+M (Msign extended) If C=1, PC<=PC+M (Msign extended) If Z=1, PC<=PC+M (Msign extended) A&M=>Z, M7=>N, M6=>V A&M=>Z, M7=>N, M6=>V A&M=>Z, M7=>N, M6=>V A&M=>Z, M7=>N, M6=>V A&M=>Z, M7=>N, M6=>V If N=1, PC<=PC+M (Msign extended) If Z=0, PC<=PC+M (Msign extended) If N=0, PC<=PC+M (Msign extended) PC<=PC+M (Msign extended) Set B, push PC & PSR, PC<=(FFFE), Set 1 If V=0, PC<=PC+M (Msign extended) If V=1, PC<=PC+M (Msign extended) C<=0 D<=0 I<=0 V<=0 A-M=>N, Z, C A-M=>N, Z, C A-M=>N, Z, C A-M=>N, Z, C A-M=>N, Z, C A-M=>N, Z, C A-M=>N, Z, C A-M=>N, Z, C A-M=>N, Z, C X-M=>N, Z, C X-M=>N, Z, C X-M=>N, Z, C Y-M=>N, Z, C Y-M=>N, Z, C
76 76 76 76 76 + + + + + + + + + + + + + + 0 -
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
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Preliminary
Name CPY DEC DEC DEC DEC DEC DEX DEY EOR EOR EOR EOR EOR EOR EOR EOR EOR INC INC INC INC INC INX INY JMP JMP JMP JSR LDA LDA LDA LDA LDA LDA LDA LDA Opcode CC C6 D6 CE DE 3A CA 88 49 45 55 4D 5D 59 52 41 51 E6 F6 EE FE 1A E8 C8 4C 6C 7C 20 A9 A5 B5 AD BD B9 B2 A1 Addr Mode ABS ZPG ZPX ABS ABX ACC IMP IMP IMM ZPG ZPX ABS ABX ABY IND INX INY ZPG ZPX ABS ABX ACC IMP IMP ABS ABI AIX ABS IMM ZPG ZPX ABS ABX ABY IND INX Flags NVEBDI ZC + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + No. Bytes 3 2 2 3 3 1 1 1 2 2 2 3 3 3 2 2 2 2 2 3 3 1 1 1 3 3 3 3 2 2 2 3 3 3 2 2 No. Cyc. 4 5 6 6 7 2 2 2 2 3 4 4 4 4 5 6 5 5 6 6 7 2 2 2 3 5 5 6 2 3 4 4 4 4 5 6 Y-M=>N, Z, C M<=M -1 M<=M -1 M<=M -1 M<=M -1 A<=A -1 X<=X -1 Y<=Y -1 A<=A^M A<=A^M A<=A^M A<=A^M A<=A^M A<=A^M A<=A^M A<=A^M A<=A^M M<=M+1 M<=M+1 M<=M+1 M<=M+1 A<=A+1 X<=X+1 Y<=Y+1 PCHT9580
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Preliminary
Name LDA LDX LDX LDX LDX LDX LDY LDY LDY LDY LDY LSR LSR LSR LSR LSR NOP ORA ORA ORA ORA ORA ORA ORA ORA ORA PHA PHP PHX PHY PLA PLP PLX PLY RMB0 RMB1 Opcode B1 A2 A6 B6 AE BE A0 A4 B4 AC BC 4A 46 56 4E 5E EA 09 05 15 0D 1D 19 12 01 11 48 08 DA 5A 68 28 FA 7A 07 17 Addr Mode INY IMM ZPG ZPY ABS ABY IMM ZPG ZPX ABS ABX ACC ZPG ZPX ABS ABX IMP IMM ZPG ZPX ABS ABX ABY IND INX INY IMP IMP IMP IMP IMP IMP IMP IMP ZPG ZPG + + Flags NVEBDI ZC + + + + + + + + + + + 0 0 0 0 0 + + + + + + + + + + + + + + + + + + + + + No. Bytes 2 2 2 2 3 3 2 2 2 3 3 1 2 2 3 3 1 2 2 2 3 3 3 2 2 2 1 1 1 1 1 1 + + 1 1 2 2 No. Cyc. 5 2 3 4 4 4 2 3 4 4 4 2 5 6 6 7 2 2 3 4 4 4 4 5 6 5 3 3 3 3 3 3 3 3 4 4 A<=M X<=M X<=M X<=M X<=M X<=M Y<=M Y<=M Y<=M Y<=M Y<=M Description
HT9580
++ ++ ++ ++ ++ + + + + + + + + + + -
M<=M>1 shift right 1, zero ->7, 0->C M<=M>1 shift right 1, zero ->7, 0->C M<=M>1 shift right 1, zero ->7, 0->C M<=M>1 shift right 1, zero ->7, 0->C M<=M>1 shift right 1, zero ->7, 0->C No operation A<=A|M A<=A|M A<=A|M A<=A|M A<=A|M A<=A|M A<=A|M A<=A|M A<=A|M Push A on stack Push status on stack Push X on stack Push Y on stack Pull A from stack Pull status from stack Pull X from stack Pull Y from stack M(0) <=0 (RMW) M(1) <=0 (RMW)
From Stack -
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Preliminary
Name RMB2 RMB3 RMB4 RMB5 RMB6 RMB7 ROL ROL ROL ROL ROL ROR ROR ROR ROR ROR RTI RTS SBC SBC SBC SBC SBC SBC SBC SBC SBC SEC SED SEI SMB0 SMB1 SMB2 SMB3 SMB4 SMB5 Opcode 27 37 47 57 67 77 2A 26 36 2E 3E 6A 66 76 6E 7E 40 60 E9 E5 F5 ED FD F9 F2 E1 F1 38 F8 78 87 97 A7 B7 C7 D7 Addr Mode ZPG ZPG ZPG ZPG ZPG ZPG ACC ZPG ZPX ABS ABX ACC ZPG ZPX ABS ABX IMP IMP IMM ZPG ZPX ABS ABX ABY IND INX INY IMP IMP IMP ZPG ZPG ZPG ZPG ZPG ZPG Flags NVEBDI ZC + + + + + + + + + + No. Bytes 2 2 2 2 2 2 1 2 2 3 3 1 2 2 3 3 1 1 2 2 2 3 3 3 3 3 3 1 1 1 2 2 2 2 2 2 No. Cyc. 4 4 4 4 4 4 2 5 6 6 7 2 5 6 6 7 5 5 2 3 4 4 4 4 5 6 5 2 2 2 4 4 4 4 4 4 Description M(2) <=0 (RMW) M(3) <=0 (RMW) M(4) <=0 (RMW) M(5) <=0 (RMW) M(6) <=0 (RMW) M(7) <=0 (RMW)
HT9580
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
M<=M<<1, rotate left 1, c<-7, 0<-C M<=M<<1, rotate left 1, c<-7, 0<-C M<=M<<1, rotate left 1, c<-7, 0<-C M<=M<<1, rotate left 1, c<-7, 0<-C M<=M<<1, rotate left 1, c<-7, 0<-C M<=M<<1, rotate right 1, c<-7, 0<-C M<=M<<1, rotate right 1, c<-7, 0<-C M<=M<<1, rotate right 1, c<-7, 0<-C M<=M<<1, rotate right 1, c<-7, 0<-C M<=M<<1, rotate right 1, c<-7, 0<-C PC<=from stack, B=0 PC<=from stack A<=A-M-C (C is a borrow) A<=A-M-C (C is a borrow) A<=A-M-C (C is a borrow) A<=A-M-C (C is a borrow) A<=A-M-C (C is a borrow) A<=A-M-C (C is a borrow) A<=A-M-C (C is a borrow) A<=A-M-C (C is a borrow) A<=A-M-C (C is a borrow) C<=1 D<=1 I<=1 M(0) <=1 (RMW) M(1) <=1 (RMW) M(2) <=1 (RMW) M(3) <=1 (RMW) M(4) <=1 (RMW) M(5) <=1 (RMW)
From Stack 1 1 -
++ ++ ++ ++ ++ ++ ++ ++ ++ -
++ ++ ++ ++ ++ ++ ++ ++ ++ 1 -
56
April 28, 2000
Preliminary
Name SMB6 SMB7 STA STA STA STA STA STA STA STX STX STX STY STY STY STZ STZ STZ STZ TAX TAY TRB TRB TSB TSB TSX TXA TXS TYA Opcode E7 F7 85 95 8D 9D 99 81 91 86 96 8E 84 94 8C 64 74 9C 9E AA A8 14 1C 04 0C BA 8A 9A 98 Addr Mode ZPG ZPG ZPG ZPX ABS ABX ABY INX INY ZPG ZPY ABS ZPG ZPX ABS ZPG ZPX ABS ABX IMP IMP ZPG ABS ZPG ABS IMP IMP IMP IMP Flags NVEBDI ZC + + + + + + + + + + + + + + No. Bytes 2 2 2 2 3 3 3 2 2 2 2 3 2 2 3 2 2 3 3 1 1 2 3 2 3 1 1 1 1 No. Cyc. 4 4 3 4 4 4 4 6 5 3 4 4 3 4 4 3 4 4 5 2 2 5 6 6 7 2 2 2 2 Description M(6) <=1 (RMW) M(7) <=1 (RMW) M<=A M<=A M<=A M<=A M<=A M<=A M<=A M<=X M<=X M<=X M<=Y M<=Y M<=Y M<=0 M<=0 M<=0 M<=0 X<=A Y<=A M<=!A&M, Z=A&M M<=!A&M, Z=A&M M<=A|M, Z=A&M M<=A|M, Z=A&M X<=S A<=X S<=X A<=Y
HT9580
57
April 28, 2000
Preliminary
Opcode Matrix
The table below shows the matrix of M6502 opcodes:
LSB MSB 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 BRK imp BPL rel JSR abs BMI rel RTI imp BVC rel RTS imp BVS rel BRA rel BCC rel LDY imm BCS rel CPY imm BNE rel CPX imm BEQ rel 1 ORA inx ORA iny AND inx AND iny EOR inx EOR iny ADC inx ADC iny STA inx STA iny LDA inx LDA iny CMP inx CMP iny SBC inx SBC iny SBC ind CMP ind CPX zpg STA ind LDX imm LDA ind ADC ind EOR ind STZ zpg STZ zpx STY zpg STY zpx LDY zpg LDY zpx CPY zpg AND ind ORA ind 2 3 4 TSB zpg TRB zpg BIT zpg BIT zpx 5 ORA zpg ORA zpx AND zpg AND zpx EOR zpg EOR zpx ADC zpg ADC zpx STA zpg STA zpx LDA zpg LDA zpx CMP zpg CMP zpx SBC zpg SBC zpx 6 ASL zpg ASL zpx ROL zpg ROL zpx LSR zpg LSR zpx ROR zpg ROR zpx STX zpg STX zpy LDX zpg LDX zpy DEC zpg DEC zpx INC zpg INC zpx 7 RB0 zpg RB1 zpg RB2 zpg RB3 zpg RB4 zpg RB5 zpg RB6 zpg RB7 zpg SB0 zpg SB1 zpg SB2 zpg SB3 zpg SB4 zpg SB5 zpg SB6 zpg SB7 zpg 8 PHP imp CLC imp PLP imp SEC imp PHA imp CLI imp PLA imp SEI imp DEY imp TYA imp TAY imp CLV imp INY imp CLD imp INX imp SED imp 9 ORA imm ORA aby AND imm AND aby EOR imm EOR aby ADC imm ADC aby BIT imm STA aby LDA imm LDA aby CMP imm CMP aby SBC imm SBC aby A ASL acc INC acc ROL acc DEC acc LSR acc PHY imp ROR acc PLY imp TXA imp TXS imp TAX imp TSX imp DEX imp PHX imp NOP imp PLX imp CPX abs JMP abi JMP aix STY abs STZ abs LDY abs LDY abx CPY abs B C TSB abs TRB abs BIT abs BIT abx JMP abs D ORA abs ORA abx AND abs AND abx EOR abs EOR abx ADC abs ADC abx STA abs STA abx LDA abs LDA abx CMP abs CMP abx SBC abs SBC abx
HT9580
E ASL abs ASL abx ROL abs ROL abx LSR abs LSR abx ROR abs ROR abx STX abs STZ abx LDX abs LDX aby DEC abs DEC abx INC abs INC abx
F BR0 zpg BR1 zpg BR2 zpg BR3 zpg BR4 zpg BR5 zpg BR6 zpg BR7 zpg BS0 zpg BS1 zpg BS2 zpg BS3 zpg BS4 zpg BS5 zpg BS6 zpg BS7 zpg
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April 28, 2000
Preliminary
Application Note
HT9580
The LCD_CTRL and LCD_CMD registers are used to control the LCD Drivers. The following example shows how to initiate the MC141803 LCD driver. The following bit settings are used for the LCD_CTRL register. ; ************ ; * LCD CONTROL * ; ************ chip1 chip0 clk cmod cs1 cs0 a0 rw LCDCT SET SET SET SET SET SET SET SET 7 6 5 4 3 2 1 0 ; select HD66410 series LCD driver 1:HD; chip0 dont care ; select SED15X (KSX)/MC141X series LCD driver 0:SED, 1:MC ; LCD clock output selection ; Just for MC141X series ; enable/disable LCD_CL ; control master LCD driver chip select ; control slave LCD driver chip select ; Data/Command select 1:display data on D0~D7 ;Data/Command select 0:display control data on D0~D7 ; LCD Read/Write input 0:WRITE 1:READ ; LCD Control register ; LCD Command register EQU 17h
LCDCM EQU 18h
The following three macros define three different modes including LCD COMMAND WRITE, LCD DATA WRITE and LCD DATA READ modes. ; *************************** ; LCDM COMMAND MODE ; LCD_A0=0 command mode ; LCD_WRB=0 write mode ; COMMAND store to ACC ; *************************** LCD_C MACRO RMB RMB STA SMB ENDM a0, LCDCT rw, LCDCT LCDCM rw, LCDCT
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April 28, 2000
Preliminary
; *************************** ; LCDM WRITE MODE ; LCD_A0=1 data mode ; LCD_WRB=0 write mode ; DATA store to ACC ; *************************** LCD_W MACRO SMB RMB STA RMB SMB ENDM ; *************************** ; LCDM READ MODE ; LCD_A0=1 data mode : LCD_WRB=1 read mode ; DATA store to ACC ; *************************** LCD_R MACRO SMB SMB LDA RMB ENDM a0, LCDCT rw, LCDCT LCDCM a0, LCDCT a0, LCDCT rw, LCDCT LCDCM a0, LCDCT rw, LCDCT
HT9580
60
April 28, 2000
Preliminary
The following subroutine will initiate the MC141803 LCD driver. ; *************************** ; * initial LCDM * ; *************************** INI_LCDM: LDA STA LDA LDA LDA LDA LDA LDA LDA LDA LDA LDA LDA LDA LDA LDA LDA #01011001B LCDCT #76H #7BH #7FH #2BH #2DH #31H #2FH #33H #29H #36H #0H #04H #37H #0H #3DH ; MC141X series LCD driver ; enable LCD_CL, LCD_CL=32kHz ; LCD_CS0 (master) enable ; normal operation ; set external clock ; feed clock in OSC2 from LCD_CL ; set oscillator enable ; set DC/DC converter on ; set internal regulator on ; set internal contrast control on ; set internal voltage divider on ; set 50kHz to get frame frequency ; set display on ; master clear GDDRAM ; dummy write data ; change to page 5 if want to clear icon line ; master clear icons ; dummy write data ; set display with icon line
61
HT9580
LCD_C LCD_C LCD_C LCD_C LCD_C LCD_C LCD_C LCD_C LCD_C LCD_C LCD_W LCD_C LCD_C LCD_W
April 28, 2000
Preliminary
LCD_C LDA LDA LDA RTS #0 #23H #83H ; set page 0 ; set col0 to seg119 ; set GDDRAM column address 3 LCD_C LCD_C LCD_C
HT9580
62
April 28, 2000
Preliminary
HT9580
Holtek Semiconductor Inc. (Headquarters) No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C. Tel: 886-3-563-1999 Fax: 886-3-563-1189 Holtek Semiconductor Inc. (Taipei Office) 5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C. Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline) Holtek Semiconductor (Hong Kong) Ltd. RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Copyright a 2000 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
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April 28, 2000

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